linux-kernel - [PATCH v8 05/15] arm64: dts: renesas: r9a07g0{4,5}4: Add POEG nodes

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Message-ID: <20251121160842.371922-6-biju.das.jz@bp.renesas.com>
Date: Fri, 21 Nov 2025 16:08:12 +0000
From: Biju <biju.das.au@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
	linux-renesas-soc@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
	Biju Das <biju.das.au@...il.com>
Subject: [PATCH v8 05/15] arm64: dts: renesas: r9a07g0{4,5}4: Add POEG nodes

From: Biju Das <biju.das.jz@...renesas.com>

Add POEGG{A,B,C,D} nodes to RZ/{G2L,V2L} SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
---
v8:
 * New patch
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 52 ++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 52 ++++++++++++++++++++++
 2 files changed, 104 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index bd52d60bafb9..28ef5ac98712 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -359,6 +359,58 @@ gpt: pwm@...48000 {
 			status = "disabled";
 		};
 
+		poegga: poeg@...48800 {
+			compatible = "renesas,r9a07g044-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10048800 0 0x400>;
+			interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_POEG_A_CLKP>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_POEG_A_RST>;
+			renesas,poeg-id = <0>;
+			renesas,gpt = <&gpt>;
+			status = "disabled";
+		};
+
+		poeggb: poeg@...48c00 {
+			compatible = "renesas,r9a07g044-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10048c00 0 0x400>;
+			interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_POEG_B_CLKP>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_POEG_B_RST>;
+			renesas,poeg-id = <1>;
+			renesas,gpt = <&gpt>;
+			status = "disabled";
+		};
+
+		poeggc: poeg@...49000 {
+			compatible = "renesas,r9a07g044-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10049000 0 0x400>;
+			interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_POEG_C_CLKP>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_POEG_C_RST>;
+			renesas,poeg-id = <2>;
+			renesas,gpt = <&gpt>;
+			status = "disabled";
+		};
+
+		poeggd: poeg@...49400 {
+			compatible = "renesas,r9a07g044-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10049400 0 0x400>;
+			interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G044_POEG_D_RST>;
+			renesas,poeg-id = <3>;
+			renesas,gpt = <&gpt>;
+			status = "disabled";
+		};
+
 		ssi0: ssi@...49c00 {
 			compatible = "renesas,r9a07g044-ssi",
 				     "renesas,rz-ssi";
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 4e0256d3201d..14ea99d2cfd0 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -359,6 +359,58 @@ gpt: pwm@...48000 {
 			status = "disabled";
 		};
 
+		poegga: poeg@...48800 {
+			compatible = "renesas,r9a07g054-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10048800 0 0x400>;
+			interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_POEG_A_CLKP>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G054_POEG_A_RST>;
+			renesas,poeg-id = <0>;
+			renesas,gpt = <&gpt>;
+			status = "disabled";
+		};
+
+		poeggb: poeg@...48c00 {
+			compatible = "renesas,r9a07g054-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10048c00 0 0x400>;
+			interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_POEG_B_CLKP>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G054_POEG_B_RST>;
+			renesas,poeg-id = <1>;
+			renesas,gpt = <&gpt>;
+			status = "disabled";
+		};
+
+		poeggc: poeg@...49000 {
+			compatible = "renesas,r9a07g054-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10049000 0 0x400>;
+			interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_POEG_C_CLKP>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G054_POEG_C_RST>;
+			renesas,poeg-id = <2>;
+			renesas,gpt = <&gpt>;
+			status = "disabled";
+		};
+
+		poeggd: poeg@...49400 {
+			compatible = "renesas,r9a07g054-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10049400 0 0x400>;
+			interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_POEG_D_CLKP>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G054_POEG_D_RST>;
+			renesas,poeg-id = <3>;
+			renesas,gpt = <&gpt>;
+			status = "disabled";
+		};
+
 		ssi0: ssi@...49c00 {
 			compatible = "renesas,r9a07g054-ssi",
 				     "renesas,rz-ssi";
-- 
2.43.0