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Message-ID: <20251121160842.371922-15-biju.das.jz@bp.renesas.com>
Date: Fri, 21 Nov 2025 16:08:21 +0000
From: Biju <biju.das.au@...il.com>
To: Uwe Kleine-König <ukleinek@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Linus Walleij <linus.walleij@...aro.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
linux-kernel@...r.kernel.org,
linux-pwm@...r.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
Biju Das <biju.das.au@...il.com>,
linux-renesas-soc@...r.kernel.org,
linux-gpio@...r.kernel.org
Subject: [DO NOT APPLY PATCH v8 14/15] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT on dead time error
From: Biju Das <biju.das.jz@...renesas.com>
Add support for output disable request from gpt, when dead time
error occurred.
Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
---
drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 19 +++++++++++++++++++
include/linux/pinctrl/rzg2l-poeg.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
index f66f69c5b1f7..d59e18832adf 100644
--- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
+++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
@@ -92,6 +92,9 @@ static void rzg2l_poeg_config_irq(struct rzg2l_poeg_chip *chip)
if (test_bit(RZG2L_GPT_OABLF, chip->gpt_irq))
rzg2l_gpt_poeg_disable_req_both_low(chip->gpt_dev, chip->index, true);
+
+ if (test_bit(RZG2L_GPT_DTEF, chip->gpt_irq))
+ rzg2l_gpt_poeg_disable_req_deadtime_error(chip->gpt_dev, chip->index, true);
}
static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr)
@@ -353,6 +356,9 @@ static int rzg2l_poeg_probe(struct platform_device *pdev)
case POEG_GPT_BOTH_LOW:
assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true);
break;
+ case POEG_GPT_DEAD_TIME:
+ assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true);
+ break;
case POEG_EXT_PIN_CTRL:
rzg2l_poeg_write(chip, POEGG_PIDE);
break;
@@ -360,6 +366,19 @@ static int rzg2l_poeg_probe(struct platform_device *pdev)
assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true);
assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true);
break;
+ case POEG_GPT_BOTH_HIGH_DEAD_TIME:
+ assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true);
+ assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true);
+ break;
+ case POEG_GPT_BOTH_LOW_DEAD_TIME:
+ assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true);
+ assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true);
+ break;
+ case POEG_GPT_ALL:
+ assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true);
+ assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true);
+ assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true);
+ break;
default:
ret = -EINVAL;
goto err_pm;
diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg2l-poeg.h
index ed3e08f10834..5edf719c155d 100644
--- a/include/linux/pinctrl/rzg2l-poeg.h
+++ b/include/linux/pinctrl/rzg2l-poeg.h
@@ -9,6 +9,7 @@
#define RZG2L_POEG_GPT_CFG_IRQ_CMD 2
#define RZG2L_POEG_GPT_FAULT_CLR_CMD 3
+#define RZG2L_GPT_DTEF 0
#define RZG2L_GPT_OABHF 1
#define RZG2L_GPT_OABLF 2
--
2.43.0
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