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Message-ID: <CAMuHMdX41rq-sd6_g1oCrQVPpgb-MXakpJ9mEbS0K+FY8Q7NDg@mail.gmail.com>
Date: Fri, 21 Nov 2025 17:28:42 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Biju <biju.das.au@...il.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby <jirislaby@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, Biju Das <biju.das.jz@...renesas.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, linux-kernel@...r.kernel.org,
linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v3 01/13] dt-bindings: serial: renesas,rsci: Document
RZ/G3E support
Hi Biju,
On Fri, 14 Nov 2025 at 11:52, Biju <biju.das.au@...il.com> wrote:
> From: Biju Das <biju.das.jz@...renesas.com>
>
> Add documentation for the serial communication interface (RSCI) found on
> the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
> to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
> to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
> has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
> (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
>
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -10,17 +10,16 @@ maintainers:
> - Geert Uytterhoeven <geert+renesas@...der.be>
> - Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> -allOf:
> - - $ref: serial.yaml#
> -
> properties:
> compatible:
> oneOf:
> - - items:
> - - const: renesas,r9a09g087-rsci # RZ/N2H
> - - const: renesas,r9a09g077-rsci # RZ/T2H
> + - enum:
> + - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> + - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
I can't find the non-FIFO ports in the documentation?
Do you mean "Selectable to 1-stage register or 32-stage FIFO"?
Isn't that software configuration instead of hardware description?
> + - renesas,r9a09g077-rsci # RZ/T2H
>
> - items:
> + - const: renesas,r9a09g087-rsci # RZ/N2H
> - const: renesas,r9a09g077-rsci # RZ/T2H
>
> reg:
> @@ -42,14 +41,36 @@ properties:
>
> clocks:
> minItems: 2
> - maxItems: 3
> + maxItems: 6
>
> clock-names:
> - minItems: 2
> + oneOf:
> + - items:
> + - const: operation
> + - const: bus
> + - const: sck # optional external clock input
> +
> + minItems: 2
> +
> + - items:
> + - const: bus
Figure 7.3-1 ("RSCI Block Diagram") calls this "pclk".
> + - const: tclk
> + - const: tclk_div64
> + - const: tclk_div16
> + - const: tclk_div4
Perhaps reverse the order of the last three, for simpler handling
in the driver: each successive clock divides by four? (yes, I know
SCI_FCK is not immediately followed by SCI_FCK_DIV* in the driver)
> + - const: sck # optional external clock input
> +
> + minItems: 5
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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