linux-kernel - Re: [PATCH v2 5/6] clk: qcom: Add TCSR clock driver for Kaanapali

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Message-ID: <a4ac2816-0a39-4d35-8136-6a4f38122219@oss.qualcomm.com>
Date: Fri, 21 Nov 2025 22:56:32 +0530
From: Taniya Das <taniya.das@....qualcomm.com>
To: Jingyi Wang <jingyi.wang@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: aiqun.yu@....qualcomm.com, Ajit Pandey <ajit.pandey@....qualcomm.com>,
        Imran Shaik <imran.shaik@....qualcomm.com>,
        Jagadeesh Kona <jagadeesh.kona@....qualcomm.com>,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 5/6] clk: qcom: Add TCSR clock driver for Kaanapali



On 11/18/2025 12:14 PM, Jingyi Wang wrote:
>> +
>> +static struct clk_branch tcsr_pcie_0_clkref_en = {
>> +	.halt_reg = 0x0,
>> +	.halt_check = BRANCH_HALT_DELAY,
>> +	.clkr = {
>> +		.enable_reg = 0x0,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(const struct clk_init_data) {
>> +			.name = "tcsr_pcie_0_clkref_en",
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
> Hi Taniya,
> 
> Here is a discussion for tcsr in this thread:
> https://lore.kernel.org/all/01de9616-825b-4fbb-83cf-
> e0bf91e8cf39@....qualcomm.com/
> 
> As TCSR_CLKS is a part of tcsr block, we should merge it as one node, the address
> should be start at 0x01fc0000 instead of 0x01fd5044, so offset need to be added in the
> tcsrcc reg configuration.
> 

Yes, the next patch will incorporate the changes in offsets of the
clocks and the device tree node needs to be updated.

-- 
Thanks,
Taniya Das