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Message-ID: <20251121080629.444992-1-aik@amd.com>
Date: Fri, 21 Nov 2025 19:06:24 +1100
From: Alexey Kardashevskiy <aik@....com>
To: <linux-kernel@...r.kernel.org>
CC: <linux-crypto@...r.kernel.org>, Tom Lendacky <thomas.lendacky@....com>,
John Allen <john.allen@....com>, Herbert Xu <herbert@...dor.apana.org.au>,
"David S. Miller" <davem@...emloft.net>, Ashish Kalra <ashish.kalra@....com>,
Joerg Roedel <joro@...tes.org>, Suravee Suthikulpanit
<suravee.suthikulpanit@....com>, Will Deacon <will@...nel.org>, Robin Murphy
<robin.murphy@....com>, "Borislav Petkov (AMD)" <bp@...en8.de>, Kim Phillips
<kim.phillips@....com>, Jerry Snitselaar <jsnitsel@...hat.com>, Vasant Hegde
<vasant.hegde@....com>, Jason Gunthorpe <jgg@...pe.ca>, Gao Shiyuan
<gaoshiyuan@...du.com>, Sean Christopherson <seanjc@...gle.com>, "Nikunj A
Dadhania" <nikunj@....com>, Michael Roth <michael.roth@....com>, Amit Shah
<amit.shah@....com>, Peter Gonda <pgonda@...gle.com>,
<iommu@...ts.linux.dev>, Alexey Kardashevskiy <aik@....com>
Subject: [PATCH kernel v2 0/5] PCI/TSM: Enabling core infrastructure on
Here are some patches to begin enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastructure
is being developed in collaboration with Intel+ARM+RiscV. There is
Documentation/driver-api/pci/tsm.rst with proposed phases:
1. IDE: encrypt PCI, host only
2. TDISP: lock + accept flow, host and guest, interface report
3. Enable secure MMIO + DMA: IOMMUFD, KVM changes
4. Device attestation: certificates, measurements
This is phase1 == IDE only.
SEV TIO spec:
https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/58271.pdf
Acronyms:
TEE - Trusted Execution Environments, a concept of managing trust
between the host and devices
TSM - TEE Security Manager (TSM), an entity which ensures security on
the host
PSP - AMD platform secure processor (also "ASP", "AMD-SP"), acts as TSM
on AMD.
SEV TIO - the TIO protocol implemented by the PSP and used by the host
GHCB - guest/host communication block - a protocol for guest-to-host
communication via a shared page
TDISP - TEE Device Interface Security Protocol (PCIe).
Flow:
- Boot host OS, load CCP which registers itself as a TSM
- PCI TSM creates sysfs nodes under "tsm" subdirectory in for all
TDISP-capable devices
- Enable IDE via "echo tsm0 >
/sys/bus/pci/devices/0000:e1:00.0/tsm/connect"
- observe "secure" in stream states in "lspci" for the rootport and endpoint
This is pushed out to
https://github.com/AMDESE/linux-kvm/commits/tsm-staging
The full "WIP" trees and configs are here:
https://github.com/AMDESE/AMDSEV/blob/tsm/stable-commits
The previous conversation is here:
https://lore.kernel.org/r/20251111063819.4098701-1-aik@amd.com
https://lore.kernel.org/r/20250218111017.491719-1-aik@amd.com
This is based on sha1
f7ae6d4ec652 Dan Williams "PCI/TSM: Add 'dsm' and 'bound' attributes for dependent functions".
Please comment. Thanks.
Alexey Kardashevskiy (5):
ccp: Make snp_reclaim_pages and __sev_do_cmd_locked public
psp-sev: Assign numbers to all status codes and add new
iommu/amd: Report SEV-TIO support
crypto: ccp: Enable SEV-TIO feature in the PSP when supported
crypto/ccp: Implement SEV-TIO PCIe IDE (phase1)
drivers/crypto/ccp/Kconfig | 1 +
drivers/crypto/ccp/Makefile | 8 +
drivers/crypto/ccp/sev-dev-tio.h | 142 ++++
drivers/crypto/ccp/sev-dev.h | 9 +
drivers/iommu/amd/amd_iommu_types.h | 1 +
include/linux/amd-iommu.h | 2 +
include/linux/psp-sev.h | 17 +-
include/uapi/linux/psp-sev.h | 66 +-
drivers/crypto/ccp/sev-dev-tio.c | 863 ++++++++++++++++++++
drivers/crypto/ccp/sev-dev-tsm.c | 405 +++++++++
drivers/crypto/ccp/sev-dev.c | 69 +-
drivers/iommu/amd/init.c | 9 +
12 files changed, 1556 insertions(+), 36 deletions(-)
create mode 100644 drivers/crypto/ccp/sev-dev-tio.h
create mode 100644 drivers/crypto/ccp/sev-dev-tio.c
create mode 100644 drivers/crypto/ccp/sev-dev-tsm.c
--
2.51.1
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