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Message-ID: <aSAsvfRrDxSLI2v9@hu-qianyu-lv.qualcomm.com>
Date: Fri, 21 Nov 2025 01:11:25 -0800
From: Qiang Yu <qiang.yu@....qualcomm.com>
To: Manivannan Sadhasivam <mani@...nel.org>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>,
Wenbin Yao <wenbin.yao@....qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Subject: Re: [PATCH v6 0/3] Add support for Glymur PCIe Gen5 x4
On Thu, Nov 20, 2025 at 04:50:12PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Nov 20, 2025 at 02:46:41AM -0800, Qiang Yu wrote:
> > On Tue, Nov 18, 2025 at 10:40:59PM +0530, Vinod Koul wrote:
> > > On 03-11-25, 23:56, Qiang Yu wrote:
> > > > Glymur is the next generation compute SoC of Qualcomm. This patch series
> > > > aims to add support for the fourth, fifth and sixth PCIe instance on it.
> > > > The fifth PCIe instance on Glymur has a Gen5 4-lane PHY and fourth, fifth
> > > > and sixth PCIe instance have a Gen5 2-lane PHY.
> > > >
> > > > The device tree changes and whatever driver patches that are not part of
> > > > this patch series will be posted separately after official announcement of
> > > > the SOC.
> > >
> > > Please rebase on phy/next, this does not apply for me
> >
> > Hi Vinod
> >
> > This patch serie depends on
> > https://lore.kernel.org/all/20251017045919.34599-2-krzysztof.kozlowski@linaro.org/
> >
>
> Why was this dependency not mentioned in the cover letter?
I mentioned it in the change history, but it was not very obvious. I will
note this and explicitly mention dependencies in the cover letter body in
other patches.
- Qiang Yu
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