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Message-Id: <20251121-glymur_llcc_enablement-v1-4-336b851b8dcb@oss.qualcomm.com>
Date: Fri, 21 Nov 2025 15:23:55 +0530
From: Pankaj Patil <pankaj.patil@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Pankaj Patil <pankaj.patil@....qualcomm.com>,
sibi.sankar@....qualcomm.com, rajendra.nayak@....qualcomm.com
Subject: [PATCH 4/4] soc: qcom: llcc-qcom: Add support for Glymur
Add system cache table(SCT) and configs for Glymur SoC
Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
---
drivers/soc/qcom/llcc-qcom.c | 207 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 13e174267294..1abfda7a58f2 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -182,6 +182,197 @@ enum llcc_reg_offset {
LLCC_TRP_WRS_CACHEABLE_EN,
};
+static const struct llcc_slice_config glymur_data[] = {
+ {
+ .usecase_id = LLCC_CPUSS,
+ .slice_id = 1,
+ .max_cap = 7680,
+ .priority = 1,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_VIDSC0,
+ .slice_id = 2,
+ .max_cap = 512,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_AUDIO,
+ .slice_id = 6,
+ .max_cap = 1024,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_VIDSC1,
+ .slice_id = 4,
+ .max_cap = 512,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_CMPT,
+ .slice_id = 10,
+ .max_cap = 7680,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_GPUHTW,
+ .slice_id = 11,
+ .max_cap = 512,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_GPU,
+ .slice_id = 9,
+ .max_cap = 7680,
+ .priority = 1,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .write_scid_en = true,
+ .write_scid_cacheable_en = true,
+ .stale_en = true,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_MMUHWT,
+ .slice_id = 18,
+ .max_cap = 768,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_AUDHW,
+ .slice_id = 22,
+ .max_cap = 1024,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_CVP,
+ .slice_id = 8,
+ .max_cap = 64,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_WRCACHE,
+ .slice_id = 31,
+ .max_cap = 1536,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_CMPTHCP,
+ .slice_id = 17,
+ .max_cap = 256,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_LCPDARE,
+ .slice_id = 30,
+ .max_cap = 768,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .alloc_oneway_en = true,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_AENPU,
+ .slice_id = 3,
+ .max_cap = 3072,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .cache_mode = 2,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_ISLAND1,
+ .slice_id = 12,
+ .max_cap = 5632,
+ .priority = 7,
+ .fixed_size = true,
+ .bonus_ways = 0x0,
+ .res_ways = 0x7FF,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_VIDVSP,
+ .slice_id = 28,
+ .max_cap = 256,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_OOBM_NS,
+ .slice_id = 5,
+ .max_cap = 512,
+ .priority = 1,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }, {
+ .usecase_id = LLCC_CPUSS_OPP,
+ .slice_id = 32,
+ .max_cap = 0,
+ .fixed_size = true,
+ .bonus_ways = 0x0,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_PCIE_TCU,
+ .slice_id = 19,
+ .max_cap = 256,
+ .priority = 1,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ .activate_on_init = true,
+ }, {
+ .usecase_id = LLCC_VIDSC_VSP1,
+ .slice_id = 29,
+ .max_cap = 256,
+ .priority = 3,
+ .fixed_size = true,
+ .bonus_ways = 0xFFF,
+ .res_ways = 0x0,
+ .vict_prio = true,
+ }
+};
+
static const struct llcc_slice_config ipq5424_data[] = {
{
.usecase_id = LLCC_CPUSS,
@@ -3872,6 +4063,16 @@ static const struct qcom_llcc_config kaanapali_cfg[] = {
},
};
+static const struct qcom_llcc_config glymur_cfg[] = {
+ {
+ .sct_data = glymur_data,
+ .size = ARRAY_SIZE(glymur_data),
+ .reg_offset = llcc_v6_reg_offset,
+ .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+ .no_edac = true,
+ },
+};
+
static const struct qcom_llcc_config qcs615_cfg[] = {
{
.sct_data = qcs615_data,
@@ -4103,6 +4304,11 @@ static const struct qcom_sct_config kaanapali_cfgs = {
.num_config = ARRAY_SIZE(kaanapali_cfg),
};
+static const struct qcom_sct_config glymur_cfgs = {
+ .llcc_config = glymur_cfg,
+ .num_config = ARRAY_SIZE(glymur_cfg),
+};
+
static const struct qcom_sct_config qcs615_cfgs = {
.llcc_config = qcs615_cfg,
.num_config = ARRAY_SIZE(qcs615_cfg),
@@ -4941,6 +5147,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_llcc_of_match[] = {
+ { .compatible = "qcom,glymur-llcc", .data = &glymur_cfgs },
{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
{ .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs},
{ .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs},
--
2.34.1
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