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Message-Id: <20251121-expressatt_nfc_accel_magn_light-v2-1-54ce493cc6cf@gmail.com>
Date: Fri, 21 Nov 2025 03:44:44 -0800
From: Rudraksha Gupta via B4 Relay <devnull+guptarud.gmail.com@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Rudraksha Gupta <guptarud@...il.com>
Subject: [PATCH v2 1/5] ARM: dts: qcom: msm8960: Add GSBI2 & GSBI7
From: Rudraksha Gupta <guptarud@...il.com>
Add the GSBI2 & GSBI7 Node, which is similar to the
other GSBI nodes in this file.
Signed-off-by: Rudraksha Gupta <guptarud@...il.com>
---
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 96 ++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 38bd4fd8dda5..fd28401cebb5 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -149,6 +149,24 @@ i2c1-pins {
};
};
+ i2c2_default_state: i2c2-default-state {
+ i2c2-pins {
+ pins = "gpio12", "gpio13";
+ function = "gsbi2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ i2c2_sleep_state: i2c2-sleep-state {
+ i2c2-pins {
+ pins = "gpio12", "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+ };
+
i2c3_default_state: i2c3-default-state {
i2c3-pins {
pins = "gpio16", "gpio17";
@@ -167,6 +185,24 @@ i2c3-pins {
};
};
+ i2c7_default_state: i2c7-default-state {
+ i2c7-pins {
+ pins = "gpio32", "gpio33";
+ function = "gsbi7";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ i2c7_sleep_state: i2c7-sleep-state {
+ i2c7-pins {
+ pins = "gpio32", "gpio33";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+ };
+
i2c8_default_state: i2c8-default-state {
i2c8-pins {
pins = "gpio36", "gpio37";
@@ -543,6 +579,36 @@ gsbi1_spi: spi@...80000 {
};
};
+ gsbi2: gsbi@...00000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16100000 0x100>;
+ ranges;
+ cell-index = <2>;
+ clocks = <&gcc GSBI2_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+
+ gsbi2_i2c: i2c@...80000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16180000 0x1000>;
+ pinctrl-0 = <&i2c2_default_state>;
+ pinctrl-1 = <&i2c2_sleep_state>;
+ pinctrl-names = "default", "sleep";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI2_QUP_CLK>,
+ <&gcc GSBI2_H_CLK>;
+ clock-names = "core",
+ "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
gsbi3: gsbi@...00000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16200000 0x100>;
@@ -600,6 +666,36 @@ gsbi5_serial: serial@...40000 {
};
};
+ gsbi7: gsbi@...00000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16600000 0x100>;
+ ranges;
+ cell-index = <7>;
+ clocks = <&gcc GSBI7_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+
+ gsbi7_i2c: i2c@...80000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16680000 0x1000>;
+ pinctrl-0 = <&i2c7_default_state>;
+ pinctrl-1 = <&i2c7_sleep_state>;
+ pinctrl-names = "default", "sleep";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI7_QUP_CLK>,
+ <&gcc GSBI7_H_CLK>;
+ clock-names = "core",
+ "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
gsbi8: gsbi@...00000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x1a000000 0x100>;
--
2.51.2
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