From fdd7aa806184f0bc8d8feb80cb2dd2c5397ee134 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 23 Nov 2025 22:29:25 +0100 Subject: [PATCH 1/2] r8169: add support for 10G SFP mode on RTL8127ATF Signed-off-by: Heiner Kallweit --- drivers/net/ethernet/realtek/r8169_main.c | 77 +++++++++++++++++++++-- drivers/net/phy/realtek/realtek_main.c | 26 ++++++++ 2 files changed, 99 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 97dbe8f8933..cbacf1ef87a 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -731,6 +731,7 @@ struct rtl8169_private { unsigned supports_gmii:1; unsigned aspm_manageable:1; unsigned dash_enabled:1; + bool sfp_mode:1; dma_addr_t counters_phys_addr; struct rtl8169_counters *counters; struct rtl8169_tc_offsets tc_offset; @@ -1094,6 +1095,10 @@ static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) if (rtl_ocp_reg_failure(reg)) return 0; + /* Return dummy MII_PHYSID2 in SFP mode to match SFP PHY driver */ + if (tp->sfp_mode && reg == (OCP_STD_PHY_BASE + 2 * MII_PHYSID2)) + return 0xcbff; + RTL_W32(tp, GPHY_OCP, reg << 15); return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? @@ -2305,6 +2310,41 @@ static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, le32_to_cpu(tp->counters->rx_unknown_opcode); } +static int rtl8169_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *cmd) +{ + struct rtl8169_private *tp = netdev_priv(ndev); + struct phy_device *phydev = tp->phydev; + int duplex = cmd->base.duplex; + int speed = cmd->base.speed; + + if (!tp->sfp_mode) + return phy_ethtool_ksettings_set(phydev, cmd); + + if (cmd->base.autoneg != AUTONEG_DISABLE) + return -EINVAL; + + if (!phy_check_valid(speed, duplex, phydev->supported)) + return -EINVAL; + + mutex_lock(&phydev->lock); + + phydev->autoneg = AUTONEG_DISABLE; + phydev->speed = speed; + phydev->duplex = duplex; + + if (phy_is_started(phydev)) { + phydev->state = PHY_UP; + phy_trigger_machine(phydev); + } else { + _phy_start_aneg(phydev); + } + + mutex_unlock(&phydev->lock); + + return 0; +} + static const struct ethtool_ops rtl8169_ethtool_ops = { .supported_coalesce_params = ETHTOOL_COALESCE_USECS | ETHTOOL_COALESCE_MAX_FRAMES, @@ -2324,7 +2364,7 @@ static const struct ethtool_ops rtl8169_ethtool_ops = { .get_eee = rtl8169_get_eee, .set_eee = rtl8169_set_eee, .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, + .set_link_ksettings = rtl8169_set_link_ksettings, .get_ringparam = rtl8169_get_ringparam, .get_pause_stats = rtl8169_get_pause_stats, .get_pauseparam = rtl8169_get_pauseparam, @@ -2436,6 +2476,34 @@ static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) clear_bit(flag, tp->wk.flags); } +static void r8127_sfp_sds_phy_reset(struct rtl8169_private *tp) +{ + RTL_W8(tp, 0x2350, RTL_R8(tp, 0x2350) & ~BIT(0)); + udelay(1); + + RTL_W16(tp, 0x233a, 0x801f); + RTL_W8(tp, 0x2350, RTL_R8(tp, 0x2350) | BIT(0)); + udelay(10); +} + +static void r8127_sfp_init_10g(struct rtl8169_private *tp) +{ + int val; + + r8127_sfp_sds_phy_reset(tp); + + RTL_W16(tp, 0x233a, 0x801a); + RTL_W16(tp, 0x233e, (RTL_R16(tp, 0x233e) & ~0x3003) | 0x1000); + + r8168_phy_ocp_write(tp, 0xc40a, 0x0000); + r8168_phy_ocp_write(tp, 0xc466, 0x0003); + r8168_phy_ocp_write(tp, 0xc808, 0x0000); + r8168_phy_ocp_write(tp, 0xc80a, 0x0000); + + val = r8168_phy_ocp_read(tp, 0xc804); + r8168_phy_ocp_write(tp, 0xc804, (val & ~0x000f) | 0x000c); +} + static void rtl8169_init_phy(struct rtl8169_private *tp) { r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); @@ -2452,6 +2520,9 @@ static void rtl8169_init_phy(struct rtl8169_private *tp) tp->pci_dev->subsystem_device == 0xe000) phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); + if (tp->sfp_mode) + r8127_sfp_init_10g(tp); + /* We may have called phy_speed_down before */ phy_speed_up(tp->phydev); @@ -5460,13 +5531,11 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) } tp->aspm_manageable = !rc; - /* Fiber mode on RTL8127AF isn't supported */ if (rtl_is_8125(tp)) { u16 data = r8168_mac_ocp_read(tp, 0xd006); if ((data & 0xff) == 0x07) - return dev_err_probe(&pdev->dev, -ENODEV, - "Fiber mode not supported\n"); + tp->sfp_mode = true; } tp->dash_type = rtl_get_dash_type(tp); diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c index 67ecf3d4af2..296559dbc7f 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -1977,6 +1977,18 @@ static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) return IRQ_HANDLED; } +static int rtlgen_sfp_get_features(struct phy_device *phydev) +{ + linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + phydev->supported); + return 0; +} + +static int rtlgen_sfp_config_aneg(struct phy_device *phydev) +{ + return 0; +} + static struct phy_driver realtek_drvs[] = { { PHY_ID_MATCH_EXACT(0x00008201), @@ -2212,6 +2224,20 @@ static struct phy_driver realtek_drvs[] = { .write_page = rtl821x_write_page, .read_mmd = rtl822x_read_mmd, .write_mmd = rtl822x_write_mmd, + }, { + PHY_ID_MATCH_EXACT(0x001ccbff), + .name = "Realtek SFP PHY Mode", + .flags = PHY_IS_INTERNAL, + .probe = rtl822x_probe, + .get_features = rtlgen_sfp_get_features, + .config_aneg = rtlgen_sfp_config_aneg, + .read_status = rtl822x_read_status, + .suspend = genphy_suspend, + .resume = rtlgen_resume, + .read_page = rtl821x_read_page, + .write_page = rtl821x_write_page, + .read_mmd = rtl822x_read_mmd, + .write_mmd = rtl822x_write_mmd, }, { PHY_ID_MATCH_EXACT(0x001ccad0), .name = "RTL8224 2.5Gbps PHY", -- 2.52.0