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Message-ID: <CAMuHMdVZznFdttha8L_r7O6rHYqrcumvJU8Fb7DaTCv6_SCnKg@mail.gmail.com>
Date: Mon, 24 Nov 2025 16:28:45 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH] clk: renesas: r9a09g077: Propagate rate changes through
mux parents
On Fri, 21 Nov 2025 at 10:09, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Enable CLK_SET_RATE_PARENT for mux clocks so that rate changes can properly
> propagate to their parent clocks. Several clocks in the R9A09G077 CPG tree
> depend on upstream PLL or divider outputs being recalculated when a child
> requests a new frequency. Without this flag, rate adjustments stop at the
> mux layer, leaving parent rates unchanged and preventing the clock tree
> from converging on the intended values.
>
> Set the flag in DEF_MUX to ensure that parent clocks participate in rate
> negotiation, which is required for correct operation of the display and
> peripheral related clocks being added for RZ/T2H support.
>
> Fixes: 065fe720eec6e ("clk: renesas: Add support for R9A09G077 SoC")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk for v6.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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