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Message-ID: <CAMuHMdWuiB5Vystj10VX4hjdvCj3DwsXNu5vz_3EXRR3mmtbbQ@mail.gmail.com>
Date: Mon, 24 Nov 2025 17:14:45 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v3] clk: renesas: r9a09g077: Add xSPI core and module clocks
Hi Prabhakar,
On Mon, 17 Nov 2025 at 21:57, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Add core clocks and module clock definitions required by the xSPI
> (Expanded SPI) IP on the R9A09G077 SoC.
>
> Define the new SCKCR fields FSELXSPI0/FSELXSPI1 and DIVSEL_XSPI0/1 and
> add two new core clocks XSPI_CLK0 and XSPI_CLK1. The xSPI block uses
> PCLKH as its bus clock (use as module clock parent) while the operation
> clock (XSPI_CLKn) is derived from PLL4. To support this arrangement
> provide mux/div selectors and divider tables for the supported
> XSPI operating rates.
>
> Add CLK_TYPE_RZT2H_FSELXSPI to implement a custom divider/mux clock
> where the determine_rate() callback enforces the hardware constraint:
> when the parent output is 600MHz only dividers 8 and 16 are valid,
> whereas for 800MHz operation the full divider set (6,8,16,32,64) may
> be used. The custom determine_rate() picks the best parent/divider pair
> to match the requested rate and programs the appropriate SCKCR fields.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> Note this patch was originally part of series [0] as rest of the series
> is already merged into linux-next, sending only this patch as v3.
> [0] https://lore.kernel.org/all/20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> v2->v3:
> - Dropped check for 800/600 MHz in
> r9a09g077_cpg_fselxspi_determine_rate() instead compared divider values 3/4.
> - Sorted pll4d1_div3/pll4d1_div4 definitions to be with other pll4d1 dividers.
> - Dropped u64 caset in DIV_ROUND_UP_ULL()
> - Hardcoded the maxdiv when no dividers are found
> - Rebaesed to latest -next
Thanks for the update!
> --- a/drivers/clk/renesas/r9a09g077-cpg.c
> +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> @@ -58,11 +60,16 @@
> #define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2)
> #define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2)
>
> +#define FSELXSPI0 CONF_PACK(SCKCR, 0, 3)
> +#define FSELXSPI1 CONF_PACK(SCKCR, 8, 3)
> +#define DIVSEL_XSPI0 CONF_PACK(SCKCR, 6, 1)
> +#define DIVSEL_XSPI1 CONF_PACK(SCKCR, 14, 1)
> #define SEL_PLL CONF_PACK(SCKCR, 22, 1)
Moving all of these up while applying, so SCKCR comes before SCKCR2.
>
> enum rzt2h_clk_types {
> CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */
> CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */
> + CLK_TYPE_RZT2H_FSELXSPI, /* Clock with FSELXSPIn source selector */
> };
>
> #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
> @@ -148,6 +172,8 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
> sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
>
> DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
> + DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1),
> + DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1),
Inserting a blank line.
> DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
> dtable_24_25_30_32),
> DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
> +static int r9a09g077_cpg_fselxspi_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + unsigned long parent_rate, best = 0, now;
> + const struct clk_div_table *clkt;
> + unsigned long rate = req->rate;
> + unsigned int num_parents;
> + unsigned int divselxspi;
> + unsigned int div = 0;
> +
> + if (!rate)
> + rate = 1;
> +
> + /* Get the number of parents for FSELXSPIn */
> + num_parents = clk_hw_get_num_parents(req->best_parent_hw);
> +
> + for (clkt = divider->table; clkt->div; clkt++) {
> + parent_rate = clk_hw_round_rate(req->best_parent_hw, rate * clkt->div);
> + /* Skip if parent can't provide any valid rate */
> + if (!parent_rate)
> + continue;
> +
> + /* Determine which DIVSELXSPIn divider (3 or 4) provides this parent_rate */
> + divselxspi = r9a09g077_cpg_fselxspi_get_divider(req->best_parent_hw, parent_rate,
> + num_parents);
> + if (!divselxspi)
> + continue;
> +
> + /*
> + * DIVSELXSPIx supports 800MHz and 600MHz operation.
> + * When divselxspi is 4 (600MHz operation), only FSELXSPIn dividers of 8 and 16
> + * are supported. Otherwise, when divselxspi is 3 (800MHz operation),
> + * dividers of 6, 8, 16, 32, and 64 are supported. This check ensures that
> + * FSELXSPIx is set correctly based on hardware limitations.
> + */
> + if (divselxspi == 4 && (clkt->div != 8 && clkt->div != 16))
> + continue;
Inserting a blank line.
> + now = DIV_ROUND_UP_ULL(parent_rate, clkt->div);
> + if (abs(rate - now) < abs(rate - best)) {
> + div = clkt->div;
> + best = now;
> + req->best_parent_rate = parent_rate;
> + }
> + }
> +
> + if (!div) {
> + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, 1);
> + divselxspi = r9a09g077_cpg_fselxspi_get_divider(req->best_parent_hw,
> + req->best_parent_rate,
> + num_parents);
> + /* default to divider 3 which will result DIVSELXSPIn = 800 MHz */
> + if (!divselxspi)
> + divselxspi = 3;
Inserting a blank line.
> + /*
> + * Use the maximum divider based on the parent clock rate:
> + * - 64 when DIVSELXSPIx is 800 MHz (divider = 3)
> + * - 16 when DIVSELXSPIx is 600 MHz (divider = 4)
> + */
> + if (divselxspi == 3)
> + div = 64;
> + else
> + div = 16;
Replacing by:
div = divselxspi == 3 ? 64 : 16;
> + }
> +
> + req->rate = DIV_ROUND_UP_ULL(req->best_parent_rate, div);
> +
> + return 0;
> +}
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk for v6.20, with the above changes.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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