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Message-ID: <20251124163211.54994-1-ziyao@disroot.org>
Date: Mon, 24 Nov 2025 16:32:08 +0000
From: Yao Zi <ziyao@...root.org>
To: Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Yao Zi <ziyao@...root.org>,
Frank <Frank.Sae@...or-comm.com>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Vladimir Oltean <vladimir.oltean@....com>,
Choong Yong Liang <yong.liang.choong@...ux.intel.com>,
Chen-Yu Tsai <wens@...e.org>,
Jisheng Zhang <jszhang@...nel.org>,
Furong Xu <0x1207@...il.com>
Cc: linux-kernel@...r.kernel.org,
netdev@...r.kernel.org,
Mingcong Bai <jeffbai@...c.io>,
Kexy Biscuit <kexybiscuit@...c.io>
Subject: [PATCH net-next v3 0/3] Add DWMAC glue driver for Motorcomm YT6801
This series adds glue driver for Motorcomm YT6801 PCIe ethernet
controller, which is considered mostly compatible with DWMAC-4 IP by
inspecting the register layout[1]. It integrates a Motorcomm YT8531S PHY
(confirmed by reading PHY ID) and GMII is used to connect the PHY to
MAC[2].
The initialization logic of the MAC is mostly based on previous upstream
effort for the controller[3] and the Deepin-maintained downstream Linux
driver[4] licensed under GPL-2.0 according to its SPDX headers. However,
this series is a completely re-write of the previous patch series,
utilizing the existing DWMAC4 driver and introducing a glue driver only.
This series only aims to add basic networking functions for the
controller, features like WoL, RSS and LED control are omitted for now.
Testing is done on Loongson 3A5000 machine. Through a local GbE switch,
it reaches 869Mbps (TX)/943Mbps (RX) on average,
## YT6801 TX
Connecting to host 172.16.70.12, port 5201
[ 5] local 172.16.70.230 port 43802 connected to 172.16.70.12 port 5201
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 102 MBytes 858 Mbits/sec 0 335 KBytes
[ 5] 1.00-2.00 sec 103 MBytes 867 Mbits/sec 0 441 KBytes
[ 5] 2.00-3.00 sec 103 MBytes 863 Mbits/sec 0 441 KBytes
[ 5] 3.00-4.00 sec 104 MBytes 870 Mbits/sec 0 441 KBytes
[ 5] 4.00-5.00 sec 104 MBytes 869 Mbits/sec 0 441 KBytes
[ 5] 5.00-6.00 sec 104 MBytes 869 Mbits/sec 0 591 KBytes
[ 5] 6.00-7.00 sec 104 MBytes 876 Mbits/sec 0 629 KBytes
[ 5] 7.00-8.00 sec 105 MBytes 878 Mbits/sec 0 629 KBytes
[ 5] 8.00-9.00 sec 104 MBytes 872 Mbits/sec 0 629 KBytes
[ 5] 9.00-10.00 sec 104 MBytes 871 Mbits/sec 0 629 KBytes
## YT6801 RX
Connecting to host 172.16.70.230, port 5201
[ 5] local 172.16.70.12 port 60866 connected to 172.16.70.230 port 5201
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 113 MBytes 949 Mbits/sec 0 352 KBytes
[ 5] 1.00-2.00 sec 113 MBytes 945 Mbits/sec 0 352 KBytes
[ 5] 2.00-3.00 sec 112 MBytes 938 Mbits/sec 0 352 KBytes
[ 5] 3.00-4.00 sec 113 MBytes 945 Mbits/sec 0 352 KBytes
[ 5] 4.00-5.00 sec 112 MBytes 938 Mbits/sec 0 407 KBytes
[ 5] 5.00-6.00 sec 112 MBytes 940 Mbits/sec 0 407 KBytes
[ 5] 6.00-7.00 sec 113 MBytes 945 Mbits/sec 0 436 KBytes
[ 5] 7.00-8.00 sec 112 MBytes 941 Mbits/sec 0 436 KBytes
[ 5] 8.00-9.00 sec 113 MBytes 947 Mbits/sec 0 645 KBytes
[ 5] 9.00-10.00 sec 112 MBytes 939 Mbits/sec 0 645 KBytes
This series depends on v5 of series "Unify platform suspend/resume
routines for PCI DWMAC glue"[5] for a clean apply. It has been some time
since I sent v1 of the series, I'm sorry for the delay. Many thanks for
your time and review.
[1]: https://lore.kernel.org/all/Z_T6vv013jraCzSD@shell.armlinux.org.uk/
[2]: https://lore.kernel.org/all/a48d76ac-db08-46d5-9528-f046a7b541dc@motor-comm.com/
[3]: https://lore.kernel.org/all/a48d76ac-db08-46d5-9528-f046a7b541dc@motor-comm.com/
[4]: https://github.com/deepin-community/kernel/tree/dc61248a0e21/drivers/net/ethernet/motorcomm/yt6801
[5]: https://lore.kernel.org/netdev/20251124160417.51514-1-ziyao@disroot.org/
Changed from v2
- Rebase on top of next-20251124
- Switch to stmmac_plat_dat_alloc() then drop now redundant parameters
from motorcomm_default_plat_data()
- Set STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP
- Add a comment indicating the possible source of CSR clock
- Link to v2: https://lore.kernel.org/netdev/20251111105252.53487-1-ziyao@disroot.org/
Changed from v1
- Drop (original) PATCH 1, add no vendor ID entry to linux/pci_ids.h
- Use PHY_INTERFACE_MODE_GMII instead of PHY_INTERFACE_MODE_INTERNAL
- Drop extra register read in motorcomm_efuse_read_byte()
- Rename EPHY_RESET to EPHY_MDIO_PHY_RESET, add a comment to reflect its
function better
- Use the newly-introduced generic PCI suspend/resume routines
- Generate a random MAC address instead of failing to probe when no MAC
address is programmed in eFuse (seen on some OEM EVBs).
- Collect Tested-by tags
- Link to v1: https://lore.kernel.org/netdev/20251014164746.50696-2-ziyao@disroot.org/
Yao Zi (3):
net: phy: motorcomm: Support YT8531S PHY in YT6801 Ethernet controller
net: stmmac: Add glue driver for Motorcomm YT6801 ethernet controller
MAINTAINERS: Assign myself as maintainer of Motorcomm DWMAC glue
driver
MAINTAINERS | 6 +
drivers/net/ethernet/stmicro/stmmac/Kconfig | 9 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../ethernet/stmicro/stmmac/dwmac-motorcomm.c | 378 ++++++++++++++++++
drivers/net/phy/motorcomm.c | 4 +
5 files changed, 398 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
--
2.51.2
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