linux-kernel - RE: [PATCH v5 3/7] vfio/nvgrace-gpu: Add support for huge pfnmap

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Message-ID:
 <CH3PR12MB7548D60ADF0FDB0589ACCDA3ABD0A@CH3PR12MB7548.namprd12.prod.outlook.com>
Date: Mon, 24 Nov 2025 18:08:00 +0000
From: Shameer Kolothum <skolothumtho@...dia.com>
To: Ankit Agrawal <ankita@...dia.com>, "jgg@...pe.ca" <jgg@...pe.ca>, Yishai
 Hadas <yishaih@...dia.com>, "kevin.tian@...el.com" <kevin.tian@...el.com>,
	"alex@...zbot.org" <alex@...zbot.org>, Aniket Agashe <aniketa@...dia.com>,
	Vikram Sethi <vsethi@...dia.com>, Matt Ochs <mochs@...dia.com>
CC: "Yunxiang.Li@....com" <Yunxiang.Li@....com>, "yi.l.liu@...el.com"
	<yi.l.liu@...el.com>, "zhangdongdong@...incomputing.com"
	<zhangdongdong@...incomputing.com>, Avihai Horon <avihaih@...dia.com>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>, "peterx@...hat.com"
	<peterx@...hat.com>, "pstanner@...hat.com" <pstanner@...hat.com>, Alistair
 Popple <apopple@...dia.com>, "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Neo Jia
	<cjia@...dia.com>, Kirti Wankhede <kwankhede@...dia.com>, "Tarun Gupta
 (SW-GPU)" <targupta@...dia.com>, Zhi Wang <zhiw@...dia.com>, Dan Williams
	<danw@...dia.com>, Dheeraj Nigam <dnigam@...dia.com>, Krishnakant Jaju
	<kjaju@...dia.com>
Subject: RE: [PATCH v5 3/7] vfio/nvgrace-gpu: Add support for huge pfnmap



> -----Original Message-----
> From: Ankit Agrawal <ankita@...dia.com>
> Sent: 24 November 2025 11:59
> To: Ankit Agrawal <ankita@...dia.com>; jgg@...pe.ca; Yishai Hadas
> <yishaih@...dia.com>; Shameer Kolothum <skolothumtho@...dia.com>;
> kevin.tian@...el.com; alex@...zbot.org; Aniket Agashe
> <aniketa@...dia.com>; Vikram Sethi <vsethi@...dia.com>; Matt Ochs
> <mochs@...dia.com>
> Cc: Yunxiang.Li@....com; yi.l.liu@...el.com;
> zhangdongdong@...incomputing.com; Avihai Horon <avihaih@...dia.com>;
> bhelgaas@...gle.com; peterx@...hat.com; pstanner@...hat.com; Alistair
> Popple <apopple@...dia.com>; kvm@...r.kernel.org; linux-
> kernel@...r.kernel.org; Neo Jia <cjia@...dia.com>; Kirti Wankhede
> <kwankhede@...dia.com>; Tarun Gupta (SW-GPU) <targupta@...dia.com>;
> Zhi Wang <zhiw@...dia.com>; Dan Williams <danw@...dia.com>; Dheeraj
> Nigam <dnigam@...dia.com>; Krishnakant Jaju <kjaju@...dia.com>
> Subject: [PATCH v5 3/7] vfio/nvgrace-gpu: Add support for huge pfnmap
> 
> From: Ankit Agrawal <ankita@...dia.com>
> 
> NVIDIA's Grace based systems have large device memory. The device
> memory is mapped as VM_PFNMAP in the VMM VMA. The nvgrace-gpu
> module could make use of the huge PFNMAP support added in mm [1].
> 
> To achieve this, nvgrace-gpu module is updated to implement huge_fault ops.
> The implementation establishes mapping according to the order request.
> Note that if the PFN or the VMA address is unaligned to the order, the
> mapping fallbacks to the PTE level.
> 
> Link: https://lore.kernel.org/all/20240826204353.2228736-1-
> peterx@...hat.com/ [1]
> 
> cc: Alex Williamson <alex@...zbot.org>
> cc: Jason Gunthorpe <jgg@...pe.ca>
> cc: Vikram Sethi <vsethi@...dia.com>
> Signed-off-by: Ankit Agrawal <ankita@...dia.com>
> ---
>  drivers/vfio/pci/nvgrace-gpu/main.c | 43 +++++++++++++++++++++++------
>  1 file changed, 35 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-
> gpu/main.c
> index f74f3d8e1ebe..c84c01954c9e 100644
> --- a/drivers/vfio/pci/nvgrace-gpu/main.c
> +++ b/drivers/vfio/pci/nvgrace-gpu/main.c
> @@ -130,32 +130,58 @@ static void nvgrace_gpu_close_device(struct
> vfio_device *core_vdev)
>  	vfio_pci_core_close_device(core_vdev);
>  }
> 
> -static vm_fault_t nvgrace_gpu_vfio_pci_fault(struct vm_fault *vmf)
> +static vm_fault_t nvgrace_gpu_vfio_pci_huge_fault(struct vm_fault *vmf,
> +						  unsigned int order)
>  {
>  	struct vm_area_struct *vma = vmf->vma;
>  	struct nvgrace_gpu_pci_core_device *nvdev = vma->vm_private_data;
>  	int index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT -
> PAGE_SHIFT);
>  	vm_fault_t ret = VM_FAULT_SIGBUS;
>  	struct mem_region *memregion;
> -	unsigned long pgoff, pfn;
> +	unsigned long pgoff, pfn, addr;
> 
>  	memregion = nvgrace_gpu_memregion(index, nvdev);
>  	if (!memregion)
>  		return ret;
> 
> -	pgoff = (vmf->address - vma->vm_start) >> PAGE_SHIFT;
> +	addr = vmf->address & ~((PAGE_SIZE << order) - 1);
> +	pgoff = (addr - vma->vm_start) >> PAGE_SHIFT;
>  	pfn = PHYS_PFN(memregion->memphys) + pgoff;
> 
> +	if (order && (addr < vma->vm_start ||
> +		      addr + (PAGE_SIZE << order) > vma->vm_end ||
> +		      pfn & ((1 << order) - 1)))
> +		return VM_FAULT_FALLBACK;
> +
>  	scoped_guard(rwsem_read, &nvdev->core_device.memory_lock)
> -		ret = vmf_insert_pfn(vmf->vma, vmf->address, pfn);
> +		ret = vfio_pci_vmf_insert_pfn(vmf, pfn, order);
> 
>  	return ret;
>  }
> 
> +static vm_fault_t nvgrace_gpu_vfio_pci_fault(struct vm_fault *vmf)
> +{
> +	return nvgrace_gpu_vfio_pci_huge_fault(vmf, 0);
> +}
> +
>  static const struct vm_operations_struct nvgrace_gpu_vfio_pci_mmap_ops =
> {
>  	.fault = nvgrace_gpu_vfio_pci_fault,
> +#ifdef CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP
> +	.huge_fault = nvgrace_gpu_vfio_pci_huge_fault,
> +#endif
>  };
> 
> +static size_t nvgrace_gpu_aligned_devmem_size(size_t memlength)
> +{
> +#ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP
> +	return ALIGN(memlength, PMD_SIZE);
> +#endif
> +#ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP
> +	return ALIGN(memlength, PUD_SIZE);
> +#endif

I think all this should be ALIGN_DOWN to be safe.

Thanks,
Shameer

> +	return memlength;
> +}
> +
>  static int nvgrace_gpu_mmap(struct vfio_device *core_vdev,
>  			    struct vm_area_struct *vma)
>  {
> @@ -185,10 +211,10 @@ static int nvgrace_gpu_mmap(struct vfio_device
> *core_vdev,
>  		return -EOVERFLOW;
> 
>  	/*
> -	 * Check that the mapping request does not go beyond available
> device
> -	 * memory size
> +	 * Check that the mapping request does not go beyond the exposed
> +	 * device memory size.
>  	 */
> -	if (end > memregion->memlength)
> +	if (end > nvgrace_gpu_aligned_devmem_size(memregion-
> >memlength))
>  		return -EINVAL;
> 
>  	vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND |
> VM_DONTDUMP);
> @@ -258,7 +284,8 @@ nvgrace_gpu_ioctl_get_region_info(struct vfio_device
> *core_vdev,
> 
>  	sparse->nr_areas = 1;
>  	sparse->areas[0].offset = 0;
> -	sparse->areas[0].size = memregion->memlength;
> +	sparse->areas[0].size =
> +		nvgrace_gpu_aligned_devmem_size(memregion-
> >memlength);
>  	sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP;
>  	sparse->header.version = 1;
> 
> --
> 2.34.1