Message-ID: <df712591-397e-422b-b9c9-fbf080cad9aa@sirena.org.uk>
Date: Mon, 24 Nov 2025 20:12:56 +0000
From: Mark Brown <broonie@...nel.org>
To: Peter Maydell <peter.maydell@...aro.org>
Cc: Marc Zyngier <maz@...nel.org>, Oliver Upton <oliver.upton@...ux.dev>,
	Joey Gouly <joey.gouly@....com>,
	Catalin Marinas <catalin.marinas@....com>,
	Suzuki K Poulose <suzuki.poulose@....com>,
	Will Deacon <will@...nel.org>, Paolo Bonzini <pbonzini@...hat.com>,
	Jonathan Corbet <corbet@....net>, Shuah Khan <shuah@...nel.org>,
	Dave Martin <Dave.Martin@....com>, Fuad Tabba <tabba@...gle.com>,
	Mark Rutland <mark.rutland@....com>,
	linux-arm-kernel@...ts.infradead.org, kvmarm@...ts.linux.dev,
	linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
	linux-doc@...r.kernel.org, linux-kselftest@...r.kernel.org,
	Eric Auger <eric.auger@...hat.com>
Subject: Re: [PATCH v8 11/29] KVM: arm64: Document the KVM ABI for SME

On Mon, Nov 24, 2025 at 03:48:06PM +0000, Peter Maydell wrote:
> On Tue, 2 Sept 2025 at 12:45, Mark Brown <broonie@...nel.org> wrote:

> > SME, the Scalable Matrix Extension, is an arm64 extension which adds
> > support for matrix operations, with core concepts patterned after SVE.

> I haven't actually tried writing any code that uses this proposed
> ABI, but mostly it looks OK to me. I have a few nits below, but
> my main concern is the bits of text that say (or seem to say --
> maybe I'm misinterpreting them) that various parts of how userspace
> accesses the guest state (e.g. the fp regs) depend on the current
> state of the vcpu, rather than being only a function of how the
> vcpu was configured. That seems to me like it's unnecessarily awkward.
> (More detail below.)

That was deliberate and I agree it is awkward, it was introduced as a
result of earlier review comments.  I had originally implemented an ABI
where the VL for the vector registers was the maximum of the SVE and SME
VLs but the feedback was that the ABI should instead follow what the
architecture does with the vector length and potentially presence of the
vector registers depending on the current streaming mode configuration.
It sounds like you would prefer something more like what was there
originally?

> > For SME unware VMMs on systems with both SVE and SME support the SVE
> > registers may be larger than expected, this should be less disruptive
> > than on a system without SVE as they will simply ignore the high bits of
> > the registers.

> I think that since enabling SME is something the VMM has to actively
> do, it isn't a big deal that they also need to do something in the
> fp or sve register access codepaths to handle SME. You can't get
> SME by surprise (same as you can't get SVE by surprise).

Yes, it's not going to affect anything without enabling it.  I can't
remember what that was in reference to, it clearly needs an update.

> >  .. [1] These encodings are not accepted for SVE-enabled vcpus.  See
> > -       :ref:`KVM_ARM_VCPU_INIT`.
> > +       :ref:`KVM_ARM_VCPU_INIT`.  They are also not accepted when SME is
> > +       enabled without SVE and the vcpu is in streaming mode.

> Does this mean that on an SME-no-SVE VM the VMM needs to know
> if the vcpu is currently in streaming mode or not to determine
> whether to read the FP registers as fp_regs or sve regs? That
> seems unpleasant -- I was expecting this to be strictly a
> matter of how the VM was configured (as it is with SVE).

Yes, it does.

> > +arm64 SME registers have the following bit patterns:

> > +  0x6080 0000 0017 00 <n:5> <slice:5>   ZA.H[n] bits[2048*slice + 2047 : 2048*slice]
> > +  0x60XX 0000 0017 0100                 ZT0

> What's the XX here ?

Sorry, will fill that in - thanks for spotting it.

> > +  0x6060 0000 0017 fffe                 KVM_REG_ARM64_SME_VLS pseudo-register
> > +
> > +Access to Z, P or ZA register IDs where 2048 * slice >= 128 * max_vq
> > +will fail with ENOENT.  max_vq is the vcpu's maximum supported vector
> > +length in 128-bit quadwords: see [2]_ below.

> What about FFR registers ? Is their ENOENT condition the same,
> or different?

It should be the same, will update to clarify.

> > +       max_vq.  This is the maximum vector length currently available to
> > +       the guest on this vcpu, and determines which register slices are
> > +       visible through this ioctl interface.

> > +       If SME is supported then the max_vq used for the Z and P registers
> > +       while SVCR.SM is 1 this vector length will be the maximum SME
> > +       vector length available for the guest, otherwise it will be the
> > +       maximum SVE vector length available.

> I can't figure out what this paragraph is trying to say, partly
> because it seems like it might be missing some text between
> "is 1" and "this vector length".

> In any case, the "while SVCR.SM is 1" part seems odd -- I
> don't think this ABI should care about the runtime vcpu state,
> only what the vcpu's max vector lengths were configured as.
> My expectation would be that the max_vq for VMM register
> access would be the maximum of the SVE and SME vector lengths
> configured for the vcpu.

This is attempting to say that the VL for the Z and P registers (and
FFR) will vary depending on if the vCPU is in streaming mode or not if
the maximum VL for SVE and SME differs, similarly to how the Z, P and
FFR registers disappear when we are not in streaming mode in a SME only
system.

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