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Message-ID: <CAMOZA0+Bo--AeyrkMHJv384kdANLbWKc6ieubkiwyQD-r44CtA@mail.gmail.com>
Date: Mon, 24 Nov 2025 23:40:51 +0100
From: Luigi Rizzo <lrizzo@...gle.com>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: jacob.jun.pan@...ux.intel.com, rizzo.unipi@...il.com, seanjc@...gle.com,
a.manzanares@...sung.com, acme@...nel.org, axboe@...nel.dk,
baolu.lu@...ux.intel.com, bp@...en8.de, dan.j.williams@...el.com,
dave.hansen@...el.com, guang.zeng@...el.com, helgaas@...nel.org,
hpa@...or.com, iommu@...ts.linux.dev, jim.harris@...sung.com, joro@...tes.org,
kevin.tian@...el.com, kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
maz@...nel.org, mingo@...hat.com, oliver.sang@...el.com,
paul.e.luse@...el.com, peterz@...radead.org, robert.hoo.linux@...il.com,
robin.murphy@....com, x86@...nel.org
Subject: Re: [PATCH v3 00/12] Coalesced Interrupt Delivery with posted MSI
On Mon, Nov 24, 2025 at 7:59 PM Thomas Gleixner <tglx@...utronix.de> wrote:
>
> On Mon, Nov 24 2025 at 10:48, Luigi Rizzo wrote:
> > I think there is an inherent race condition when intremap=posted_msi
> > and the IRQ subsystem resends pending interrupts via __apic_send_IPI().
> > ...
...
> It sends an IPI to the actual vector, which invokes the handler
> directly. That works only once because the remap interrupt chip does not
> issue an EOI, so the vector becomes stale.... Clearly nobody ever tested
> that code.
Thanks for clarifying that the problem is the missing EOI.
> ...
> So instead of playing games with the PIR, this can be actually solved
> for both cases. See below.
Thanks, I verified that your patch fixes the problem (and also works
with software moderation)
Tested-by: Luigi Rizzo <lrizzo@...gle.com>
cheers
luigi
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