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Message-Id: <20251124111914.3187803-3-neeraj.soni@oss.qualcomm.com>
Date: Mon, 24 Nov 2025 16:49:14 +0530
From: Neeraj Soni <neeraj.soni@....qualcomm.com>
To: ulf.hansson@...aro.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, andersson@...nel.org, konradybcio@...nel.org
Cc: linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, neeraj.soni@....qualcomm.com
Subject: [PATCH 2/2] arm64: dts: qcom: kodiak: enable the inline crypto engine for SDHC
Add an ICE node to kodiak SoC description and enable it by adding a
phandle to the SDHC node.
Signed-off-by: Neeraj Soni <neeraj.soni@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index c2ccbb67f800..9d2029a906ce 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1069,6 +1069,15 @@ opp-384000000 {
opp-avg-kBps = <390000 0>;
};
};
+
+ qcom,ice = <&sdhc_ice>;
+ };
+
+ sdhc_ice: crypto@...000 {
+ compatible = "qcom,sc7280-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x007C8000 0x0 0x18000>;
+ clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
};
gpi_dma0: dma-controller@...000 {
--
2.34.1
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