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Message-ID: <20251125223001.7d05d834.zhiw@nvidia.com>
Date: Tue, 25 Nov 2025 22:30:01 +0200
From: Zhi Wang <zhiw@...dia.com>
To: <ankita@...dia.com>
CC: <jgg@...pe.ca>, <yishaih@...dia.com>, <skolothumtho@...dia.com>,
<kevin.tian@...el.com>, <alex@...zbot.org>, <aniketa@...dia.com>,
<vsethi@...dia.com>, <mochs@...dia.com>, <Yunxiang.Li@....com>,
<yi.l.liu@...el.com>, <zhangdongdong@...incomputing.com>,
<avihaih@...dia.com>, <bhelgaas@...gle.com>, <peterx@...hat.com>,
<pstanner@...hat.com>, <apopple@...dia.com>, <kvm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <cjia@...dia.com>, <kwankhede@...dia.com>,
<targupta@...dia.com>, <danw@...dia.com>, <dnigam@...dia.com>,
<kjaju@...dia.com>
Subject: Re: [PATCH v6 4/6] vfio/nvgrace-gpu: split the code to wait for GPU
ready
On Tue, 25 Nov 2025 17:30:11 +0000
<ankita@...dia.com> wrote:
Looking good to me.
Reviewed-by: Zhi Wang <zhiw@...dia.com>
> From: Ankit Agrawal <ankita@...dia.com>
>
> Split the function that check for the GPU device being ready on
> the probe.
>
> Move the code to wait for the GPU to be ready through BAR0 register
> reads to a separate function. This would help reuse the code.
>
> Reviewed-by: Shameer Kolothum <skolothumtho@...dia.com>
> Signed-off-by: Ankit Agrawal <ankita@...dia.com>
> ---
> drivers/vfio/pci/nvgrace-gpu/main.c | 29
> +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12
> deletions(-)
>
> diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c
> b/drivers/vfio/pci/nvgrace-gpu/main.c index
> 8a982310b188..2b736cb82f38 100644 ---
> a/drivers/vfio/pci/nvgrace-gpu/main.c +++
> b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -130,6 +130,20 @@ static
> void nvgrace_gpu_close_device(struct vfio_device *core_vdev)
> vfio_pci_core_close_device(core_vdev); }
>
> +static int nvgrace_gpu_wait_device_ready(void __iomem *io)
> +{
> + unsigned long timeout = jiffies +
> msecs_to_jiffies(POLL_TIMEOUT_MS); +
> + do {
> + if ((ioread32(io + C2C_LINK_BAR0_OFFSET) ==
> STATUS_READY) &&
> + (ioread32(io + HBM_TRAINING_BAR0_OFFSET) ==
> STATUS_READY))
> + return 0;
> + msleep(POLL_QUANTUM_MS);
> + } while (!time_after(jiffies, timeout));
> +
> + return -ETIME;
> +}
> +
> static unsigned long addr_to_pgoff(struct vm_area_struct *vma,
> unsigned long addr)
> {
> @@ -933,9 +947,8 @@ static bool nvgrace_gpu_has_mig_hw_bug(struct
> pci_dev *pdev)
> * Ensure that the BAR0 region is enabled before accessing the
> * registers.
> */
> -static int nvgrace_gpu_wait_device_ready(struct pci_dev *pdev)
> +static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)
> {
> - unsigned long timeout = jiffies +
> msecs_to_jiffies(POLL_TIMEOUT_MS); void __iomem *io;
> int ret = -ETIME;
>
> @@ -953,16 +966,8 @@ static int nvgrace_gpu_wait_device_ready(struct
> pci_dev *pdev) goto iomap_exit;
> }
>
> - do {
> - if ((ioread32(io + C2C_LINK_BAR0_OFFSET) ==
> STATUS_READY) &&
> - (ioread32(io + HBM_TRAINING_BAR0_OFFSET) ==
> STATUS_READY)) {
> - ret = 0;
> - goto reg_check_exit;
> - }
> - msleep(POLL_QUANTUM_MS);
> - } while (!time_after(jiffies, timeout));
> + ret = nvgrace_gpu_wait_device_ready(io);
>
> -reg_check_exit:
> pci_iounmap(pdev, io);
> iomap_exit:
> pci_release_selected_regions(pdev, 1 << 0);
> @@ -979,7 +984,7 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,
> u64 memphys, memlength;
> int ret;
>
> - ret = nvgrace_gpu_wait_device_ready(pdev);
> + ret = nvgrace_gpu_probe_check_device_ready(pdev);
> if (ret)
> return ret;
>
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