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Message-ID: <vrtz6pumfpjyis5sez7iia37yyruizl2wz3vb4ojafww5hrjev@pmy5uiknetre>
Date: Tue, 25 Nov 2025 11:25:03 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, geert+renesas@...der.be,
magnus.damm@...il.com, p.zabel@...gutronix.de, linux-pci@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>, Wolfram Sang <wsa+renesas@...g-engineering.com>
Subject: Re: [PATCH v8 5/6] arm64: dts: renesas: rzg3s-smarc: Enable PCIe
On Wed, Nov 19, 2025 at 04:35:22PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> The RZ Smarc Carrier-II board has PCIe headers mounted on it. Enable PCIe
> support.
>
> Tested-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Acked-by: Manivannan Sadhasivam <mani@...nel.org>
- Mani
> ---
>
> Changes in v8:
> - none
>
> Changes in v7:
> - none
>
> Changes in v6:
> - none
>
> Changes in v5:
> - collected tags
>
> Changes in v4:
> - none
>
> Changes in v3:
> - collected tags
>
> Changes in v2:
> - none
>
> arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> index 5e044a4d0234..6e9e78aca0b0 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> @@ -132,6 +132,12 @@ power-monitor@44 {
> };
> };
>
> +&pcie {
> + pinctrl-0 = <&pcie_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> &pinctrl {
> audio_clock_pins: audio-clock {
> pins = "AUDIO_CLK1", "AUDIO_CLK2";
> @@ -159,6 +165,11 @@ key-3-gpio-hog {
> line-name = "key-3-gpio-irq";
> };
>
> + pcie_pins: pcie {
> + pinmux = <RZG2L_PORT_PINMUX(13, 2, 2)>, /* PCIE_RST_OUT_B */
> + <RZG2L_PORT_PINMUX(13, 3, 2)>; /* PCIE_CLKREQ_B */
> + };
> +
> scif0_pins: scif0 {
> pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
> <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
> --
> 2.43.0
>
--
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