Message-Id: <20251125114847.804961-1-vladimir.oltean@nxp.com>
Date: Tue, 25 Nov 2025 13:48:32 +0200
From: Vladimir Oltean <vladimir.oltean@....com>
To: linux-phy@...ts.infradead.org
Cc: Ioana Ciornei <ioana.ciornei@....com>,
	Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	Josua Mayer <josua@...id-run.com>,
	linux-kernel@...r.kernel.org,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	devicetree@...r.kernel.org
Subject: [PATCH v5 phy 00/15] Lynx 28G improvements part 1

This is the first part in upstreaming a set of around 100 patches that
were developed in NXP's vendor Linux Factory kernel over the course of
several years.

This part is mainly concerned with correcting some historical mistakes
which make extending the driver more difficult:
- The 3 instances of this SerDes block, as seen on NXP LX2160A, need to
  be differentiated in order to reject configurations unsupported by
  hardware. The proposal is to do that based on compatible string.
- Lanes cannot have electrical parameters described in the device tree,
  because they are not described in the device tree.
- The register naming scheme forces us to modify a single register field
  per lynx_28g_lane_rmw() call - leads to inefficient code
- lynx_28g_lane_set_sgmii(), lynx_28g_lane_set_10gbaser() are unfit for
  their required roles when the current SerDes protocol is 25GBase-R.
  They are replaced with a better structured approach.
- USXGMII and 10GBase-R have different protocol converters, and should
  be treated separately by the SerDes driver.

Compared to v4 here:
https://lore.kernel.org/linux-phy/20251110092241.1306838-1-vladimir.oltean@nxp.com/
I deferred even more work to "part 2", to fit Vinod's suggestion of
removing an unnecessary memset() on lane memory into 15 patches per set.
I also removed Cc: stable, I'll handle that myself after this work is
merged.

Compared to v3 here:
https://lore.kernel.org/linux-phy/20250926180505.760089-1-vladimir.oltean@nxp.com/
there are some new patches, but it overall shrank in size because I
deferred new features to "part 2". Essentially, v4 is like v3, except
with a better plan to handle device tree transitions without breakage,
and with the following patches temporarily dropped:
[PATCH v3 phy 14/17] phy: lynx-28g: add support for 25GBASER
[PATCH v3 phy 15/17] phy: lynx-28g: use timeouts when waiting for
 lane halt and reset
[PATCH v3 phy 16/17] phy: lynx-28g: truly power the lanes up or down
[PATCH v3 phy 17/17] phy: lynx-28g: implement phy_exit() operation

Compared to v2 here:
https://lore.kernel.org/lkml/d0c8bbf8-a0c5-469f-a148-de2235948c0f@solid-run.com/
v3 grew in size due to Josua's request to avoid unbounded loops waiting
for lane resets/halts/stops to complete.

Compared to v1 here:
https://lore.kernel.org/lkml/20250904154402.300032-1-vladimir.oltean@nxp.com/
v2 grew in size due to Josua's request for a device tree binding where
individual lanes have their own OF nodes. This seems to be the right
moment to make that change.

Detailed change log in individual patches. Thanks to Josua, Rob, Conor,
Krzysztof, Ioana, Vinod who provided feedback on the previous version,
and I hope it has all been addressed.

Cc: Rob Herring <robh@...nel.org>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: Conor Dooley <conor+dt@...nel.org>
Cc: devicetree@...r.kernel.org

Ioana Ciornei (1):
  phy: lynx-28g: configure more equalization params for 1GbE and 10GbE

Vladimir Oltean (14):
  dt-bindings: phy: lynx-28g: permit lane OF PHY providers
  phy: lynx-28g: refactor lane probing to lynx_28g_probe_lane()
  phy: lynx-28g: support individual lanes as OF PHY providers
  phy: lynx-28g: avoid memsetting lane already allocated with kzalloc()
  phy: lynx-28g: remove LYNX_28G_ prefix from register names
  phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg"
    with "val" and "mask"
  phy: lynx-28g: use FIELD_GET() and FIELD_PREP()
  phy: lynx-28g: convert iowrite32() calls with magic values to macros
  phy: lynx-28g: restructure protocol configuration register accesses
  phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic
  phy: lynx-28g: refactor lane->interface to lane->mode
  phy: lynx-28g: distinguish between 10GBASE-R and USXGMII
  phy: lynx-28g: use "dev" argument more in lynx_28g_probe()
  phy: lynx-28g: improve lynx_28g_probe() sequence

 .../devicetree/bindings/phy/fsl,lynx-28g.yaml |   71 +-
 drivers/phy/freescale/phy-fsl-lynx-28g.c      | 1156 +++++++++++++----
 2 files changed, 945 insertions(+), 282 deletions(-)

-- 
2.34.1

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