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Message-ID: <20251125120559.158860-8-clamor95@gmail.com>
Date: Tue, 25 Nov 2025 14:05:54 +0200
From: Svyatoslav Ryhel <clamor95@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>,
Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Thierry Reding <treding@...dia.com>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Mikko Perttunen <mperttunen@...dia.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Dmitry Osipenko <digetx@...il.com>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Svyatoslav Ryhel <clamor95@...il.com>
Cc: linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-pm@...r.kernel.org
Subject: [PATCH v4 07/12] dt-bindings: memory: Document Tegra114 External Memory Controller
Include Tegra114 support into existing Tegra124 EMC schema with the most
notable difference being the amount of EMC timings and a few SoC unique
entries.
Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
---
.../nvidia,tegra124-emc.yaml | 174 +++---------------
1 file changed, 26 insertions(+), 148 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
index f5f03bf36413..9398aae49093 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
@@ -16,7 +16,9 @@ description: |
properties:
compatible:
- const: nvidia,tegra124-emc
+ enum:
+ - nvidia,tegra114-emc
+ - nvidia,tegra124-emc
reg:
maxItems: 1
@@ -29,6 +31,9 @@ properties:
items:
- const: emc
+ interrupts:
+ maxItems: 1
+
"#interconnect-cells":
const: 0
@@ -164,153 +169,12 @@ patternProperties:
nvidia,emc-configuration:
description:
EMC timing characterization data. These are the registers (see
- section "15.6.2 EMC Registers" in the TRM) whose values need to
+ section "20.11.2 EMC Registers" in the Tegra114 TRM or section
+ "15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to
be specified, according to the board documentation.
$ref: /schemas/types.yaml#/definitions/uint32-array
- items:
- - description: EMC_RC
- - description: EMC_RFC
- - description: EMC_RFC_SLR
- - description: EMC_RAS
- - description: EMC_RP
- - description: EMC_R2W
- - description: EMC_W2R
- - description: EMC_R2P
- - description: EMC_W2P
- - description: EMC_RD_RCD
- - description: EMC_WR_RCD
- - description: EMC_RRD
- - description: EMC_REXT
- - description: EMC_WEXT
- - description: EMC_WDV
- - description: EMC_WDV_MASK
- - description: EMC_QUSE
- - description: EMC_QUSE_WIDTH
- - description: EMC_IBDLY
- - description: EMC_EINPUT
- - description: EMC_EINPUT_DURATION
- - description: EMC_PUTERM_EXTRA
- - description: EMC_PUTERM_WIDTH
- - description: EMC_PUTERM_ADJ
- - description: EMC_CDB_CNTL_1
- - description: EMC_CDB_CNTL_2
- - description: EMC_CDB_CNTL_3
- - description: EMC_QRST
- - description: EMC_QSAFE
- - description: EMC_RDV
- - description: EMC_RDV_MASK
- - description: EMC_REFRESH
- - description: EMC_BURST_REFRESH_NUM
- - description: EMC_PRE_REFRESH_REQ_CNT
- - description: EMC_PDEX2WR
- - description: EMC_PDEX2RD
- - description: EMC_PCHG2PDEN
- - description: EMC_ACT2PDEN
- - description: EMC_AR2PDEN
- - description: EMC_RW2PDEN
- - description: EMC_TXSR
- - description: EMC_TXSRDLL
- - description: EMC_TCKE
- - description: EMC_TCKESR
- - description: EMC_TPD
- - description: EMC_TFAW
- - description: EMC_TRPAB
- - description: EMC_TCLKSTABLE
- - description: EMC_TCLKSTOP
- - description: EMC_TREFBW
- - description: EMC_FBIO_CFG6
- - description: EMC_ODT_WRITE
- - description: EMC_ODT_READ
- - description: EMC_FBIO_CFG5
- - description: EMC_CFG_DIG_DLL
- - description: EMC_CFG_DIG_DLL_PERIOD
- - description: EMC_DLL_XFORM_DQS0
- - description: EMC_DLL_XFORM_DQS1
- - description: EMC_DLL_XFORM_DQS2
- - description: EMC_DLL_XFORM_DQS3
- - description: EMC_DLL_XFORM_DQS4
- - description: EMC_DLL_XFORM_DQS5
- - description: EMC_DLL_XFORM_DQS6
- - description: EMC_DLL_XFORM_DQS7
- - description: EMC_DLL_XFORM_DQS8
- - description: EMC_DLL_XFORM_DQS9
- - description: EMC_DLL_XFORM_DQS10
- - description: EMC_DLL_XFORM_DQS11
- - description: EMC_DLL_XFORM_DQS12
- - description: EMC_DLL_XFORM_DQS13
- - description: EMC_DLL_XFORM_DQS14
- - description: EMC_DLL_XFORM_DQS15
- - description: EMC_DLL_XFORM_QUSE0
- - description: EMC_DLL_XFORM_QUSE1
- - description: EMC_DLL_XFORM_QUSE2
- - description: EMC_DLL_XFORM_QUSE3
- - description: EMC_DLL_XFORM_QUSE4
- - description: EMC_DLL_XFORM_QUSE5
- - description: EMC_DLL_XFORM_QUSE6
- - description: EMC_DLL_XFORM_QUSE7
- - description: EMC_DLL_XFORM_ADDR0
- - description: EMC_DLL_XFORM_ADDR1
- - description: EMC_DLL_XFORM_ADDR2
- - description: EMC_DLL_XFORM_ADDR3
- - description: EMC_DLL_XFORM_ADDR4
- - description: EMC_DLL_XFORM_ADDR5
- - description: EMC_DLL_XFORM_QUSE8
- - description: EMC_DLL_XFORM_QUSE9
- - description: EMC_DLL_XFORM_QUSE10
- - description: EMC_DLL_XFORM_QUSE11
- - description: EMC_DLL_XFORM_QUSE12
- - description: EMC_DLL_XFORM_QUSE13
- - description: EMC_DLL_XFORM_QUSE14
- - description: EMC_DLL_XFORM_QUSE15
- - description: EMC_DLI_TRIM_TXDQS0
- - description: EMC_DLI_TRIM_TXDQS1
- - description: EMC_DLI_TRIM_TXDQS2
- - description: EMC_DLI_TRIM_TXDQS3
- - description: EMC_DLI_TRIM_TXDQS4
- - description: EMC_DLI_TRIM_TXDQS5
- - description: EMC_DLI_TRIM_TXDQS6
- - description: EMC_DLI_TRIM_TXDQS7
- - description: EMC_DLI_TRIM_TXDQS8
- - description: EMC_DLI_TRIM_TXDQS9
- - description: EMC_DLI_TRIM_TXDQS10
- - description: EMC_DLI_TRIM_TXDQS11
- - description: EMC_DLI_TRIM_TXDQS12
- - description: EMC_DLI_TRIM_TXDQS13
- - description: EMC_DLI_TRIM_TXDQS14
- - description: EMC_DLI_TRIM_TXDQS15
- - description: EMC_DLL_XFORM_DQ0
- - description: EMC_DLL_XFORM_DQ1
- - description: EMC_DLL_XFORM_DQ2
- - description: EMC_DLL_XFORM_DQ3
- - description: EMC_DLL_XFORM_DQ4
- - description: EMC_DLL_XFORM_DQ5
- - description: EMC_DLL_XFORM_DQ6
- - description: EMC_DLL_XFORM_DQ7
- - description: EMC_XM2CMDPADCTRL
- - description: EMC_XM2CMDPADCTRL4
- - description: EMC_XM2CMDPADCTRL5
- - description: EMC_XM2DQPADCTRL2
- - description: EMC_XM2DQPADCTRL3
- - description: EMC_XM2CLKPADCTRL
- - description: EMC_XM2CLKPADCTRL2
- - description: EMC_XM2COMPPADCTRL
- - description: EMC_XM2VTTGENPADCTRL
- - description: EMC_XM2VTTGENPADCTRL2
- - description: EMC_XM2VTTGENPADCTRL3
- - description: EMC_XM2DQSPADCTRL3
- - description: EMC_XM2DQSPADCTRL4
- - description: EMC_XM2DQSPADCTRL5
- - description: EMC_XM2DQSPADCTRL6
- - description: EMC_DSR_VTTGEN_DRV
- - description: EMC_TXDSRVTTGEN
- - description: EMC_FBIO_SPARE
- - description: EMC_ZCAL_WAIT_CNT
- - description: EMC_MRS_WAIT_CNT2
- - description: EMC_CTT
- - description: EMC_CTT_DURATION
- - description: EMC_CFG_PIPE
- - description: EMC_DYN_SELF_REF_CONTROL
- - description: EMC_QPOP
+ minItems: 97
+ maxItems: 143
required:
- clock-frequency
@@ -318,9 +182,7 @@ patternProperties:
- nvidia,emc-auto-cal-config2
- nvidia,emc-auto-cal-config3
- nvidia,emc-auto-cal-interval
- - nvidia,emc-bgbias-ctl0
- nvidia,emc-cfg
- - nvidia,emc-cfg-2
- nvidia,emc-ctt-term-ctrl
- nvidia,emc-mode-1
- nvidia,emc-mode-2
@@ -344,6 +206,22 @@ required:
- "#interconnect-cells"
- operating-points-v2
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra124-emc
+ then:
+ patternProperties:
+ "^emc-timings-[0-9]+$":
+ patternProperties:
+ "^timing-[0-9]+$":
+ required:
+ - nvidia,emc-bgbias-ctl0
+ - nvidia,emc-cfg-2
+
additionalProperties: false
examples:
--
2.51.0
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