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Message-ID: <aScg8oH3I8wJvFHs@gen8>
Date: Wed, 26 Nov 2025 09:46:58 -0600
From: Drew Fustini <fustini@...nel.org>
To: Yao Zi <ziyao@...root.org>
Cc: Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Paul Walmsley <pjw@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Icenowy Zheng <uwu@...nowy.me>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
Han Gao <rabenda.cn@...il.com>, Han Gao <gaohan@...as.ac.cn>
Subject: Re: [PATCH 4/7] clk: thead: th1520-ap: Support setting PLL rates
On Thu, Nov 20, 2025 at 01:14:13PM +0000, Yao Zi wrote:
> TH1520 ships several PLLs that could operate in either integer or
> fractional mode. However, the TRM only lists a few configuration whose
> stability is considered guaranteed.
>
> Add a table-lookup rate determination logic to support PLL rate setting,
> and fill up frequency-configuration tables for AP-subsystem PLLs.
>
> Signed-off-by: Yao Zi <ziyao@...root.org>
> ---
> drivers/clk/thead/clk-th1520-ap.c | 142 ++++++++++++++++++++++++++++++
> 1 file changed, 142 insertions(+)
Reviewed-by: Drew Fustini <fustini@...nel.org>
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