linux-kernel - Re: [PATCH v7 1/2] drm/mediatek: Adjust bandwidth limit for DP

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Message-ID: <54b075b4ff6b9aa7cd916bb65e34e5edae3642dc.camel@mediatek.com>
Date: Wed, 26 Nov 2025 03:11:35 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: "simona@...ll.ch" <simona@...ll.ch>, Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@...iatek.com>,
	Mac Shen (沈俊) <Mac.Shen@...iatek.com>,
	"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>, "airlied@...il.com"
	<airlied@...il.com>, AngeloGioacchino Del Regno
	<angelogioacchino.delregno@...labora.com>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>, Peng Liu (刘鹏)
	<Peng.Liu@...iatek.com>, "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
	LIANKUN YANG (杨连坤) <Liankun.Yang@...iatek.com>
CC: "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-mediatek@...ts.infradead.org"
	<linux-mediatek@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v7 1/2] drm/mediatek: Adjust bandwidth limit for DP

On Mon, 2025-11-24 at 09:14 +0000, LIANKUN YANG (杨连坤) wrote:
> On Wed, 2025-11-19 at 09:18 +0000, CK Hu (胡俊光) wrote:
> > On Tue, 2025-11-04 at 16:55 +0800, Liankun Yang wrote:
> > > By adjusting the order of link training and relocating it to HPD,
> > > link training can identify the usability of each lane in the
> > > current link.
> > > 
> > > It also supports handling signal instability and weakness due to
> > > environmental issues, enabling the acquisition of a stable
> > > bandwidth
> > > for the current link. Subsequently, DP work can proceed based on
> > > the actual maximum bandwidth.
> > > 
> > > It should training in the hpd event thread.
> > > Check the mode with lane count and link rate of training.
> > > 
> > > If we're eDP and capabilities were already parsed we can skip
> > > reading again because eDP panels aren't hotpluggable hence the
> > > caps and training information won't ever change in a boot life
> > > 
> > > Therefore, bridge typec judgment is required for edp training in
> > > atomic_enable function.
> > > 
> > > The `mtk_dp_aux_panel_poweron` function fails to align.
> > > Within the `mtk_dp_hpd_event_thread`, if DP is disconnected,
> > > the `mtk_dp_aux_panel_poweron` function will write from `aux` to
> > > `DPRX`,
> > > causing a failure and thus preventing symmetry.
> > 
> > I'm curious about another case.
> > In your description, when DP plug out and plug in, DRM core would not
> > call mtk_dp_bridge_atomic_enable(), right?
> > If so, when I plug out DP, and plug in another DP panel which support
> > smaller resolution,
> > then mtk_dp_bridge_atomic_enable() is not called and below call
> > sequence would not happen:
> > 
> > mtk_dp_bridge_atomic_enable() -> mtk_dp_video_enable() ->
> > mtk_dp_set_tx_out() -> mtk_dp_setup_tu()
> > 
> > In mtk_dp_setup_tu, it would set sram_read_start according to
> > lane_count.
> > But the call sequence would not happen when new plug in, the
> > sram_read_start would be old value which may incorrect.
> > If think that when plug in and plug out, it should disable DP and
> > then enable DP again.
> > If DRM core does not do this, I think we should modify DRM core or
> > you should reconfig the whole DP when plug in, not only training.
> > 
> > Regards,
> > CK
> > 
> 
> Hi CK
> 
> When DP plug out, DRM core will call mtk_dp_bridge_atomic_disable().
> When DP plug in, DRM core will call mtk_dp_bridge_atomic_enable().


When DP plug in, DRM core will call mtk_dp_bridge_atomic_enable(), and mtk_dp_bridge_atomic_enable would call mtk_dp_training().
So it's not necessary to call mtk_dp_training() in mtk_dp_hpd_event_thread().

Regards,
CK

> 
> If DP plug in, sram_read_start will be recalculate based on the lane
> count.
> 
> Regards
> Liankun.
> 
> > 
> > > 
> > > Signed-off-by: Liankun Yang <liankun.yang@...iatek.com>
> > > ---
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_dp.c | 20 ++++++++++++++++++++
> > >  1 file changed, 20 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
> > > b/drivers/gpu/drm/mediatek/mtk_dp.c
> > > index bef6eeb30d3e..0ba2c208811c 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> > > @@ -1976,6 +1976,7 @@ static irqreturn_t
> > > mtk_dp_hpd_event_thread(int hpd, void *dev)
> > >  	struct mtk_dp *mtk_dp = dev;
> > >  	unsigned long flags;
> > >  	u32 status;
> > > +	int ret;
> > >  
> > >  	if (mtk_dp->need_debounce && mtk_dp-
> > > > train_info.cable_plugged_in)
> > >  		msleep(100);
> > > @@ -1994,9 +1995,28 @@ static irqreturn_t
> > > mtk_dp_hpd_event_thread(int hpd, void *dev)
> > >  			memset(&mtk_dp->info.audio_cur_cfg, 0,
> > >  			       sizeof(mtk_dp->info.audio_cur_cfg));
> > >  
> > > +			mtk_dp->enabled = false;
> > > +			/* power off aux */
> > > +			mtk_dp_update_bits(mtk_dp,
> > > MTK_DP_TOP_PWR_STATE,
> > > +					   DP_PWR_STATE_BANDGAP_TPLL,
> > > +					   DP_PWR_STATE_MASK);
> > > +
> > >  			mtk_dp->need_debounce = false;
> > >  			mod_timer(&mtk_dp->debounce_timer,
> > >  				  jiffies + msecs_to_jiffies(100) - 1);
> > > +		} else {
> > > +			mtk_dp_aux_panel_poweron(mtk_dp, true);
> > > +
> > > +			ret = mtk_dp_parse_capabilities(mtk_dp);
> > > +			if (ret)
> > > +				drm_err(mtk_dp->drm_dev, "Can't parse
> > > capabilities\n");
> > > +
> > > +			/* Training */
> > > +			ret = mtk_dp_training(mtk_dp);
> > > +			if (ret)
> > > +				drm_err(mtk_dp->drm_dev, "Training
> > > failed, %d\n", ret);
> > > +
> > > +			mtk_dp->enabled = true;
> > >  		}
> > >  	}
> > >  
> > 
> >