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Message-ID: <w3ezxipjucswfswfg2z7b7uyu55bssqatdnbxa6jflii4j7nym@lxsnidrewepu>
Date: Wed, 26 Nov 2025 02:09:37 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Taniya Das <taniya.das@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Ajit Pandey <ajit.pandey@....qualcomm.com>,
Imran Shaik <imran.shaik@....qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 08/11] clk: qcom: dispcc: Add support for display
clock controller Kaanapali
On Tue, Nov 25, 2025 at 11:15:17PM +0530, Taniya Das wrote:
> Support the clock controller driver for Kaanapali to enable display SW to
> be able to control the clocks.
>
> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> ---
> drivers/clk/qcom/Kconfig | 10 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/dispcc-kaanapali.c | 1956 +++++++++++++++++++++++++++++++++++
> 3 files changed, 1967 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index a284ba040b78ba2f7b7c7ead14023c0ec637f841..e293d1a816c2eece0291e9ee707698e97ed75cd8 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -46,6 +46,16 @@ config CLK_GLYMUR_TCSRCC
> Support for the TCSR clock controller on GLYMUR devices.
> Say Y if you want to use peripheral devices such as USB/PCIe/EDP.
>
> +config CLK_KAANAPALI_DISPCC
> + tristate "Kaanapali Display Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + select CLK_KAANAPALI_GCC
> + help
> + Support for the display clock controller on Qualcomm Technologies, Inc
> + Kaanapali devices.
> + Say Y if you want to support display devices and functionality such as
> + splash screen.
> +
> config CLK_X1E80100_CAMCC
> tristate "X1E80100 Camera Clock Controller"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 0ac8a9055a43230d848c6a0c1ac118c03c3e18d2..98ec8aeb5d5049855bb65f7371a10fb2418a468f 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
> obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
> obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
> obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
> +obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o
> obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
> obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
> obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
> diff --git a/drivers/clk/qcom/dispcc-kaanapali.c b/drivers/clk/qcom/dispcc-kaanapali.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..baae2ec1f72aac04b265fb62433c75e9bd425d4d
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc-kaanapali.c
> @@ -0,0 +1,1956 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,kaanapali-dispcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +#define DISP_CC_MISC_CMD 0xF000
> +
> +enum {
> + DT_BI_TCXO,
> + DT_BI_TCXO_AO,
> + DT_AHB_CLK,
> + DT_SLEEP_CLK,
> + DT_DP0_PHY_PLL_LINK_CLK,
> + DT_DP0_PHY_PLL_VCO_DIV_CLK,
> + DT_DP1_PHY_PLL_LINK_CLK,
> + DT_DP1_PHY_PLL_VCO_DIV_CLK,
> + DT_DP2_PHY_PLL_LINK_CLK,
> + DT_DP2_PHY_PLL_VCO_DIV_CLK,
> + DT_DP3_PHY_PLL_LINK_CLK,
> + DT_DP3_PHY_PLL_VCO_DIV_CLK,
> + DT_DSI0_PHY_PLL_OUT_BYTECLK,
> + DT_DSI0_PHY_PLL_OUT_DSICLK,
> + DT_DSI1_PHY_PLL_OUT_BYTECLK,
> + DT_DSI1_PHY_PLL_OUT_DSICLK,
> +};
> +
> +enum {
> + P_BI_TCXO,
> + P_DISP_CC_PLL0_OUT_MAIN,
> + P_DISP_CC_PLL1_OUT_EVEN,
> + P_DISP_CC_PLL1_OUT_MAIN,
> + P_DISP_CC_PLL2_OUT_MAIN,
> + P_DP0_PHY_PLL_LINK_CLK,
> + P_DP0_PHY_PLL_VCO_DIV_CLK,
> + P_DP1_PHY_PLL_LINK_CLK,
> + P_DP1_PHY_PLL_VCO_DIV_CLK,
> + P_DP2_PHY_PLL_LINK_CLK,
> + P_DP2_PHY_PLL_VCO_DIV_CLK,
> + P_DP3_PHY_PLL_LINK_CLK,
> + P_DP3_PHY_PLL_VCO_DIV_CLK,
> + P_DSI0_PHY_PLL_OUT_BYTECLK,
> + P_DSI0_PHY_PLL_OUT_DSICLK,
> + P_DSI1_PHY_PLL_OUT_BYTECLK,
> + P_DSI1_PHY_PLL_OUT_DSICLK,
> +};
> +
> +static const struct pll_vco pongo_eko_t_vco[] = {
> + { 38400000, 153600000, 0 },
> +};
> +
> +static const struct pll_vco taycan_eko_t_vco[] = {
> + { 249600000, 2500000000, 0 },
> +};
> +
> +/* 257.142858 MHz Configuration */
This is a bit strange frequency for the boot config.
> +static const struct alpha_pll_config disp_cc_pll0_config = {
> + .l = 0xd,
> + .cal_l = 0x48,
> + .alpha = 0x6492,
> + .config_ctl_val = 0x25c400e7,
> + .config_ctl_hi_val = 0x0a8062e0,
> + .config_ctl_hi1_val = 0xf51dea20,
> + .user_ctl_val = 0x00000008,
> + .user_ctl_hi_val = 0x00000002,
> +};
> +
--
With best wishes
Dmitry
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