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Message-ID: <aSi3C5ws5mS-6NFx@mozart.vkv.me>
Date: Thu, 27 Nov 2025 12:39:39 -0800
From: Calvin Owens <calvin@...nvd.org>
To: Jason Gunthorpe <jgg@...pe.ca>
Cc: linux-kernel@...r.kernel.org, iommu@...ts.linux.dev,
Lu Baolu <baolu.lu@...ux.intel.com>,
Nicolin Chen <nicolinc@...dia.com>, Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>,
David Woodhouse <dwmw2@...radead.org>,
Robin Murphy <robin.murphy@....com>
Subject: Re: [PATCH next] iommu/vt-d: Use shallowest supported table depth in
sagaw
On Thursday 11/27 at 14:32 -0400, Jason Gunthorpe wrote:
> On Thu, Nov 27, 2025 at 09:06:35AM -0800, Calvin Owens wrote:
> > The failing condition in paging_domain_compatible_second_stage() is:
> >
> > /* Page table level is supported. */
> > if (!(cap_sagaw(iommu->cap) & BIT(pt_info.aw)))
> > return -EINVAL;
> >
> > This happens because, for many domains on this machine, MGAW=39 but
> > SAGAW=0x04: that claims a 39-bit maximum address width, but also claims
> > to only support 48-bit/4-level paging, which seems odd.
>
> This logic was intended to deal with this:
>
> static int compute_vasz_lg2_ss(struct intel_iommu *iommu)
> {
> unsigned int sagaw = cap_sagaw(iommu->cap);
> unsigned int mgaw = cap_mgaw(iommu->cap);
>
> /*
> * Find the largest table size that both the mgaw and sagaw support.
> * This sets both the number of table levels and the valid range of
> * IOVA.
> */
> if (mgaw >= 48 && (sagaw & BIT(3)))
> return min(57, mgaw);
> else if (mgaw >= 39 && (sagaw & BIT(2)))
> return min(48, mgaw);
> else if (mgaw >= 30 && (sagaw & BIT(1)))
> return min(39, mgaw);
>
> Though it is not right..
>
> I didn't consider that this would come up, the only way to solve it is
> to pass in more information so the tree can be higher than the vasz
> requires..
>
> Can you try these two commits?
>
> https://github.com/jgunthorpe/linux/commits/iommu_pt_vtd/
That works on the Skylake machine. If you want it:
Tested-by: Calvin Owens <calvin@...nvd.org>
Thanks,
Calvin
> Thanks,
> Jason
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