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Message-ID: <c7d9f540-b1c0-45a4-befe-177b6d79277a@gmail.com>
Date: Fri, 28 Nov 2025 00:12:48 +0100
From: Anna Maniscalco <anna.maniscalco2000@...il.com>
To: Akhil P Oommen <akhilpo@....qualcomm.com>
Cc: Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>, Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jesszhan0024@...il.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Antonino Maniscalco <antomani103@...il.com>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH] drm/msm: Fix a7xx per pipe register programming
On 11/27/25 10:57 PM, Akhil P Oommen wrote:
> On 11/27/2025 5:16 AM, Anna Maniscalco wrote:
>> GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe
>> but it needs to be programmed for both.
>>
>> Program both pipes in hw_init and introducea separate reglist for it in
>> order to add this register to the dynamic reglist which supports
>> restoring registers per pipe.
>>
>> Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info")
>> Signed-off-by: Anna Maniscalco <anna.maniscalco2000@...il.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 9 ++-
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 91 +++++++++++++++++++++++++++++--
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 +++++
>> 4 files changed, 109 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 29107b362346..c8d0b1d59b68 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
>> REG_A6XX_UCHE_MODE_CNTL,
>> REG_A6XX_RB_NC_MODE_CNTL,
>> REG_A6XX_RB_CMP_DBG_ECO_CNTL,
>> - REG_A7XX_GRAS_NC_MODE_CNTL,
>> REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
>> REG_A6XX_UCHE_GBIF_GX_CONFIG,
>> REG_A6XX_UCHE_CLIENT_PF,
>> @@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] = {
>>
>> DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
>>
>> +static const struct adreno_reglist_pipe a750_reglist_pipe_regs[] = {
>> + { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
>> +};
>> +
>> +DECLARE_ADRENO_REGLIST_PIPE_LIST(a750_reglist_pipe);
>> +
>> static const struct adreno_info a7xx_gpus[] = {
>> {
>> .chip_ids = ADRENO_CHIP_IDS(0x07000200),
>> @@ -1548,6 +1553,7 @@ static const struct adreno_info a7xx_gpus[] = {
>> .protect = &a730_protect,
>> .pwrup_reglist = &a7xx_pwrup_reglist,
>> .ifpc_reglist = &a750_ifpc_reglist,
>> + .pipe_reglist = &a750_reglist_pipe,
>> .gbif_cx = a640_gbif,
>> .gmu_chipid = 0x7050001,
>> .gmu_cgc_mode = 0x00020202,
>> @@ -1590,6 +1596,7 @@ static const struct adreno_info a7xx_gpus[] = {
>> .protect = &a730_protect,
>> .pwrup_reglist = &a7xx_pwrup_reglist,
>> .ifpc_reglist = &a750_ifpc_reglist,
>> + .pipe_reglist = &a750_reglist_pipe,
>> .gbif_cx = a640_gbif,
>> .gmu_chipid = 0x7090100,
>> .gmu_cgc_mode = 0x00020202,
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index 0200a7e71cdf..b98f3e93d0a8 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -16,6 +16,72 @@
>>
>> #define GPU_PAS_ID 13
>>
>> +static void a7xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe)
>> +{
>> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> + u32 val;
>> +
>> + val = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe);
>> +
>> + if (a6xx_gpu->cached_aperture == val)
>> + return;
>> +
>> + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, val);
>> +
>> + a6xx_gpu->cached_aperture = val;
>> +}
>> +
>> +static void a7xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags)
>> +{
>> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> +
>> + spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags);
>> +
>> + a7xx_aperture_slice_set(gpu, pipe);
>> +}
>> +
>> +static void a7xx_aperture_release(struct msm_gpu *gpu, unsigned long flags)
>> +{
>> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> +
>> + spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags);
>> +}
>> +
>> +static void a7xx_aperture_clear(struct msm_gpu *gpu)
>> +{
>> + unsigned long flags;
>> +
>> + a7xx_aperture_acquire(gpu, PIPE_NONE, &flags);
>> + a7xx_aperture_release(gpu, flags);
>> +}
>> +
>> +static void a7xx_write_pipe(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 offset, u32 data)
>> +{
>> + unsigned long flags;
>> +
>> + a7xx_aperture_acquire(gpu, pipe, &flags);
>> + gpu_write(gpu, offset, data);
>> + a7xx_aperture_release(gpu, flags);
>> +}
>> +
>> +static u32 a7xx_read_pipe(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 offset)
>> +{
>> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> + unsigned long flags;
>> + u32 val;
>> +
>> + spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags);
>> + a7xx_aperture_slice_set(gpu, pipe);
>> + val = gpu_read(gpu, offset);
>> + spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags);
>> +
>> + return val;
>> +}
>> +
> All of the above helper routines are unncessary because we access only a
> single register under the aperture in a7x hw_init(). Lets drop these and
> program the aperture register directly below.
We also access (read) it in a7xx_patch_pwrup_reglist though, so do we
want to inline it twice?
>
>
>> static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu)
>> {
>> u64 count_hi, count_lo, temp;
>> @@ -849,9 +915,12 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
>> min_acc_len_64b << 3 |
>> hbb_lo << 1 | ubwc_mode);
>>
>> - if (adreno_is_a7xx(adreno_gpu))
>> - gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,
>> - FIELD_PREP(GENMASK(8, 5), hbb_lo));
>> + if (adreno_is_a7xx(adreno_gpu)) {
>> + for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++)
>> + a7xx_write_pipe(gpu, pipe_id, REG_A7XX_GRAS_NC_MODE_CNTL,
>> + FIELD_PREP(GENMASK(8, 5), hbb_lo));
>> + a7xx_aperture_clear(gpu);
>> + }
>>
>> gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
>> min_acc_len_64b << 23 | hbb_lo << 21);
>> @@ -865,9 +934,11 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
>> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> const struct adreno_reglist_list *reglist;
>> + const struct adreno_reglist_pipe_list *pipe_reglist;
>> void *ptr = a6xx_gpu->pwrup_reglist_ptr;
>> struct cpu_gpu_lock *lock = ptr;
>> u32 *dest = (u32 *)&lock->regs[0];
>> + u32 pipe_reglist_count = 0;
>> int i;
>>
>> lock->gpu_req = lock->cpu_req = lock->turn = 0;
>> @@ -907,7 +978,19 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
>> * (<aperture, shifted 12 bits> <address> <data>), and the length is
>> * stored as number for triplets in dynamic_list_len.
>> */
>> - lock->dynamic_list_len = 0;
>> + pipe_reglist = adreno_gpu->info->a6xx->pipe_reglist;
>> + for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) {
>> + for (i = 0; i < pipe_reglist->count; i++) {
>> + if (pipe_reglist->regs[i].pipe & BIT(pipe_id) == 0)
>> + continue;
>> + *dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id);
>> + *dest++ = pipe_reglist->regs[i].offset;
>> + *dest++ = a7xx_read_pipe(gpu, pipe_id,
>> + pipe_reglist->regs[i].offset);
>> + pipe_reglist_count++;
>> + }
>> + }
>> + lock->dynamic_list_len = pipe_reglist_count;
>> }
>>
>> static int a7xx_preempt_start(struct msm_gpu *gpu)
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> index 6820216ec5fc..0a1d6acbc638 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> @@ -46,6 +46,7 @@ struct a6xx_info {
>> const struct adreno_protect *protect;
>> const struct adreno_reglist_list *pwrup_reglist;
>> const struct adreno_reglist_list *ifpc_reglist;
>> + const struct adreno_reglist_pipe_list *pipe_reglist;
>> const struct adreno_reglist *gbif_cx;
>> const struct adreno_reglist_pipe *nonctxt_reglist;
>> u32 max_slices;
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> index 0f8d3de97636..cd1846c1375e 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> @@ -182,12 +182,25 @@ struct adreno_reglist_list {
>> u32 count;
>> };
>>
>> +struct adreno_reglist_pipe_list {
>> + /** @reg: List of register **/
>> + const struct adreno_reglist_pipe *regs;
>> + /** @count: Number of registers in the list **/
>> + u32 count;
>> +};
>> +
> Please move this chunk down, just above the DECLARE_ADRENO_REGLIST_PIPE_LIST
>
> -Akhil
>
>> #define DECLARE_ADRENO_REGLIST_LIST(name) \
>> static const struct adreno_reglist_list name = { \
>> .regs = name ## _regs, \
>> .count = ARRAY_SIZE(name ## _regs), \
>> };
>>
>> +#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \
>> +static const struct adreno_reglist_pipe_list name = { \
>> + .regs = name ## _regs, \
>> + .count = ARRAY_SIZE(name ## _regs), \
>> +};
>> +
>> struct adreno_gpu {
>> struct msm_gpu base;
>> const struct adreno_info *info;
>>
>> ---
>> base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530
>> change-id: 20251126-gras_nc_mode_fix-7224ee506a39
>>
>> Best regards,
Best regards,
--
Anna Maniscalco <anna.maniscalco2000@...il.com>
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