linux-kernel - RE: [Intel-wired-lan] [PATCH iwl-net v2] igc: fix race condition in TX timestamp read for register 0

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Message-ID: <IA3PR11MB8986EDF2AFFE142291974FBCE5DFA@IA3PR11MB8986.namprd11.prod.outlook.com>
Date: Thu, 27 Nov 2025 06:52:08 +0000
From: "Loktionov, Aleksandr" <aleksandr.loktionov@...el.com>
To: "Choong, Chwee Lin" <chwee.lin.choong@...el.com>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, "Kitszel, Przemyslaw"
	<przemyslaw.kitszel@...el.com>, Andrew Lunn <andrew+netdev@...n.ch>, "David S
 . Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, "Jakub
 Kicinski" <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Richard Cochran
	<richardcochran@...il.com>, "Gomes, Vinicius" <vinicius.gomes@...el.com>
CC: "intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "Shalev, Avi"
	<avi.shalev@...el.com>, "Song, Yoong Siang" <yoong.siang.song@...el.com>,
	"Choong, Chwee Lin" <chwee.lin.choong@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH iwl-net v2] igc: fix race condition in
 TX timestamp read for register 0



> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of
> Chwee-Lin Choong
> Sent: Thursday, November 27, 2025 2:49 PM
> To: Nguyen, Anthony L <anthony.l.nguyen@...el.com>; Kitszel, Przemyslaw
> <przemyslaw.kitszel@...el.com>; Andrew Lunn <andrew+netdev@...n.ch>; David
> S . Miller <davem@...emloft.net>; Eric Dumazet <edumazet@...gle.com>;
> Jakub Kicinski <kuba@...nel.org>; Paolo Abeni <pabeni@...hat.com>; Richard
> Cochran <richardcochran@...il.com>; Gomes, Vinicius
> <vinicius.gomes@...el.com>
> Cc: intel-wired-lan@...ts.osuosl.org; netdev@...r.kernel.org; linux-
> kernel@...r.kernel.org; Shalev, Avi <avi.shalev@...el.com>; Song, Yoong
> Siang <yoong.siang.song@...el.com>; Choong, Chwee Lin
> <chwee.lin.choong@...el.com>
> Subject: [Intel-wired-lan] [PATCH iwl-net v2] igc: fix race condition in
> TX timestamp read for register 0
> 
> The current HW bug workaround checks the TXTT_0 ready bit first, then
> reads TXSTMPL_0 twice (before and after reading TXSTMPH_0) to detect
> whether a new timestamp was captured by timestamp register 0 during the
> workaround.
> 
> This sequence has a race: if a new timestamp is captured after checking
> the TXTT_0 bit but before the first TXSTMPL_0 read, the detection fails
> because both the “old” and “new” values come from the same timestamp.
> 
> Fix by reading TXSTMPL_0 first to establish a baseline, then checking the
> TXTT_0 bit. This ensures any timestamp captured during the race window
> will be detected.
> 
> Old sequence:
>   1. Check TXTT_0 ready bit
>   2. Read TXSTMPL_0 (baseline)
>   3. Read TXSTMPH_0 (interrupt workaround)
>   4. Read TXSTMPL_0 (detect changes vs baseline)
> 
> New sequence:
>   1. Read TXSTMPL_0 (baseline)
>   2. Check TXTT_0 ready bit
>   3. Read TXSTMPH_0 (interrupt workaround)
>   4. Read TXSTMPL_0 (detect changes vs baseline)
> 
> Fixes: c789ad7cbebc ("igc: Work around HW bug causing missing timestamps")
> Suggested-by: Avi Shalev <avi.shalev@...el.com>
> Signed-off-by: Song Yoong Siang <yoong.siang.song@...el.com>
> Signed-off-by: Chwee-Lin Choong <chwee.lin.choong@...el.com>
> ---

...

>  export                                   |  0
>  2 files changed, 25 insertions(+), 18 deletions(-)  create mode 100644
> export
> 

...

>  	for (i = 1; i < IGC_MAX_TX_TSTAMP_REGS; i++) { diff --git a/export
> b/export new file mode 100644 index 000000000000..e69de29bb2d1
Please drop this unrelated file from the patch.
Everything else looks good for me.

Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@...el.com>

> --
> 2.43.0