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Message-ID: <0471c6a3-0fbc-45c7-afc3-e8639d7e9f5e@linaro.org>
Date: Thu, 27 Nov 2025 10:06:12 +0000
From: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To: Hangxiang Ma <hangxiang.ma@....qualcomm.com>,
Loic Poulain <loic.poulain@....qualcomm.com>, Robert Foss
<rfoss@...nel.org>, Andi Shyti <andi.shyti@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Todor Tomov <todor.too@...il.com>,
Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>
Cc: linux-i2c@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-media@...r.kernel.org, jeyaprakash.soundrapandian@....qualcomm.com,
Vijay Kumar Tumati <vijay.tumati@....qualcomm.com>
Subject: Re: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss
On 26/11/2025 09:38, Hangxiang Ma wrote:
> Add support for the camera subsystem on the SM8750 Qualcomm SoC. This
> includes bringing up the CSIPHY, CSID, VFE/RDI interfaces. This change
> also introduces the necessary modules for enabling future extended
> functionalities.
>
> The SM8750 platform provides:
> - 3 x VFE, 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE
> - 3 x CSID
> - 2 x CSID Lite
> - 6 x CSI PHY
> - 2 x ICP
> - 1 x IPE
> - 2 x JPEG DMA & Downscaler
> - 2 x JPEG Encoder
> - 1 x OFE
> - 5 x RT CDM
> - 3 x TPG
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@....qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 599 +++++++++++++++++++++++++++++++++++
> 1 file changed, 599 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 1937b48fac5a..b83389c3456b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -3332,6 +3332,605 @@ data-pins {
> bias-pull-up;
> };
> };
> +
> + cci0_0_default: cci0-0-default-state {
> + sda-pins {
> + pins = "gpio113";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio114";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci0_0_sleep: cci0-0-sleep-state {
> + sda-pins {
> + pins = "gpio113";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio114";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci0_1_default: cci0-1-default-state {
> + sda-pins {
> + pins = "gpio115";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio116";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci0_1_sleep: cci0-1-sleep-state {
> + sda-pins {
> + pins = "gpio115";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio116";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci1_0_default: cci1-0-default-state {
> + sda-pins {
> + pins = "gpio117";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio118";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci1_0_sleep: cci1-0-sleep-state {
> + sda-pins {
> + pins = "gpio117";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio118";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci1_1_default: cci1-1-default-state {
> + sda-pins {
> + pins = "gpio111";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio164";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci1_1_sleep: cci1-1-sleep-state {
> + sda-pins {
> + pins = "gpio111";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio164";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci2_0_default: cci2-0-default-state {
> + sda-pins {
> + pins = "gpio112";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio153";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci2_0_sleep: cci2-0-sleep-state {
> + sda-pins {
> + pins = "gpio112";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio153";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci2_1_default: cci2-1-default-state {
> + sda-pins {
> + pins = "gpio119";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio120";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci2_1_sleep: cci2-1-sleep-state {
> + sda-pins {
> + pins = "gpio119";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio120";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> + };
> +
> + cci0: cci@...b000 {
> + compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac7b000 0x0 0x1000>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CCI_0_CLK>;
> + clock-names = "ahb", "cci";
> + pinctrl-0 = <&cci0_0_default &cci0_1_default>;
> + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cci0_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci0_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci1: cci@...c000 {
> + compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac7c000 0x0 0x1000>;
> + interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CCI_1_CLK>;
> + clock-names = "ahb", "cci";
> + pinctrl-0 = <&cci1_0_default &cci1_1_default>;
> + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cci1_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci1_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci2: cci@...d000 {
> + compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac7d000 0x0 0x1000>;
> + interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CCI_2_CLK>;
> + clock-names = "ahb", "cci";
> + pinctrl-0 = <&cci2_0_default &cci2_1_default>;
> + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cci2_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci2_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + camss: isp@...7000 {
> + compatible = "qcom,sm8750-camss";
> +
> + reg = <0x0 0x0ad27000 0x0 0x2b00>,
> + <0x0 0x0ad2a000 0x0 0x2b00>,
> + <0x0 0x0ad2d000 0x0 0x2b00>,
> + <0x0 0x0ad6d000 0x0 0xa00>,
> + <0x0 0x0ad72000 0x0 0xa00>,
> + <0x0 0x0ada9000 0x0 0x2000>,
> + <0x0 0x0adab000 0x0 0x2000>,
> + <0x0 0x0adad000 0x0 0x2000>,
> + <0x0 0x0adaf000 0x0 0x2000>,
> + <0x0 0x0adb1000 0x0 0x2000>,
> + <0x0 0x0adb3000 0x0 0x2000>,
> + <0x0 0x0ac86000 0x0 0x10000>,
> + <0x0 0x0ac96000 0x0 0x10000>,
> + <0x0 0x0aca6000 0x0 0x10000>,
> + <0x0 0x0ad6e000 0x0 0x1800>,
> + <0x0 0x0ad73000 0x0 0x1800>,
> + <0x0 0x0ac06000 0x0 0x1000>,
> + <0x0 0x0ac05000 0x0 0x1000>,
> + <0x0 0x0ac16000 0x0 0x1000>,
> + <0x0 0x0ac15000 0x0 0x1000>,
> + <0x0 0x0ac42000 0x0 0x18000>,
> + <0x0 0x0ac26000 0x0 0x1000>,
> + <0x0 0x0ac25000 0x0 0x1000>,
> + <0x0 0x0ac28000 0x0 0x1000>,
> + <0x0 0x0ac27000 0x0 0x1000>,
> + <0x0 0x0ac2a000 0x0 0x18000>,
> + <0x0 0x0ac7f000 0x0 0x580>,
> + <0x0 0x0ac80000 0x0 0x580>,
> + <0x0 0x0ac81000 0x0 0x580>,
> + <0x0 0x0ac82000 0x0 0x580>,
> + <0x0 0x0ac83000 0x0 0x580>,
> + <0x0 0x0ad8b000 0x0 0x400>,
> + <0x0 0x0ad8c000 0x0 0x400>,
> + <0x0 0x0ad8d000 0x0 0x400>;
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "icp0",
> + "icp0_sys",
> + "icp1",
> + "icp1_sys",
> + "ipe",
> + "jpeg_dma0",
> + "jpeg_enc0",
> + "jpeg_dma1",
> + "jpeg_enc1",
> + "ofe",
> + "rt_cdm0",
> + "rt_cdm1",
> + "rt_cdm2",
> + "rt_cdm3",
> + "rt_cdm4",
> + "tpg0",
> + "tpg1",
> + "tpg2";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY5_CLK>,
> + <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_TFE_0_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_1_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_2_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
> + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
> + <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>,
> + <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
> + <&camcc CAM_CC_ICP_0_CLK>,
> + <&camcc CAM_CC_ICP_0_AHB_CLK>,
> + <&camcc CAM_CC_ICP_1_CLK>,
> + <&camcc CAM_CC_ICP_1_AHB_CLK>,
> + <&camcc CAM_CC_IPE_NPS_CLK>,
> + <&camcc CAM_CC_IPE_NPS_AHB_CLK>,
> + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IPE_PPS_CLK>,
> + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_JPEG_0_CLK>,
> + <&camcc CAM_CC_JPEG_1_CLK>,
> + <&camcc CAM_CC_OFE_AHB_CLK>,
> + <&camcc CAM_CC_OFE_ANCHOR_CLK>,
> + <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>,
> + <&camcc CAM_CC_OFE_HDR_CLK>,
> + <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>,
> + <&camcc CAM_CC_OFE_MAIN_CLK>,
> + <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_0_BAYER_CLK>,
> + <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_1_BAYER_CLK>,
> + <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_2_BAYER_CLK>,
> + <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>;
> + clock-names = "camnoc_nrt_axi",
> + "camnoc_rt_axi",
> + "camnoc_rt_vfe0",
> + "camnoc_rt_vfe1",
> + "camnoc_rt_vfe2",
> + "camnoc_rt_vfe_lite",
> + "cam_top_ahb",
> + "cam_top_fast_ahb",
> + "csid",
> + "csid_csiphy_rx",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "csiphy5",
> + "csiphy5_timer",
> + "gcc_hf_axi",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe2",
> + "vfe2_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid",
> + "qdss_debug_xo",
> + "camnoc_ipe_nps",
> + "camnoc_ofe",
> + "gcc_sf_axi",
> + "icp0",
> + "icp0_ahb",
> + "icp1",
> + "icp1_ahb",
> + "ipe_nps",
> + "ipe_nps_ahb",
> + "ipe_nps_fast_ahb",
> + "ipe_pps",
> + "ipe_pps_fast_ahb",
> + "jpeg0",
> + "jpeg1",
> + "ofe_ahb",
> + "ofe_anchor",
> + "ofe_anchor_fast_ahb",
> + "ofe_hdr",
> + "ofe_hdr_fast_ahb",
> + "ofe_main",
> + "ofe_main_fast_ahb",
> + "vfe0_bayer",
> + "vfe0_bayer_fast_ahb",
> + "vfe1_bayer",
> + "vfe1_bayer_fast_ahb",
> + "vfe2_bayer",
> + "vfe2_bayer_fast_ahb";
> +
> + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "camnoc_nrt",
> + "camnoc_rt",
> + "icp0",
> + "icp1",
> + "jpeg_dma0",
> + "jpeg_enc0",
> + "jpeg_dma1",
> + "jpeg_enc1",
> + "rt_cdm0",
> + "rt_cdm1",
> + "rt_cdm2",
> + "rt_cdm3",
> + "rt_cdm4",
> + "tpg0",
> + "tpg1",
> + "tpg2";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_mnoc",
> + "sf_icp_mnoc",
> + "sf_mnoc";
> +
> + iommus = <&apps_smmu 0x1c00 0x00>,
> + <&apps_smmu 0x18c0 0x00>,
> + <&apps_smmu 0x1980 0x00>,
> + <&apps_smmu 0x1840 0x00>,
> + <&apps_smmu 0x1800 0x00>,
> + <&apps_smmu 0x18a0 0x00>,
> + <&apps_smmu 0x1880 0x00>,
> + <&apps_smmu 0x1820 0x00>,
> + <&apps_smmu 0x1860 0x00>;
> +
> + power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
> + <&camcc CAM_CC_TFE_1_GDSC>,
> + <&camcc CAM_CC_TFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>,
> + <&camcc CAM_CC_IPE_0_GDSC>,
> + <&camcc CAM_CC_OFE_GDSC>;
> + power-domain-names = "vfe0",
> + "vfe1",
> + "vfe2",
> + "top",
> + "ipe",
> + "ofe";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + };
> + };
> +
> };
>
> tcsrcc: clock-controller@...4008 {
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
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