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Message-ID: <bcc61dc3-80ab-4ac4-b9a5-7fc42cff9ab5@oss.qualcomm.com>
Date: Thu, 27 Nov 2025 11:55:15 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>,
mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
bhelgaas@...gle.com
Cc: robh@...nel.org, linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org,
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Subject: Re: [PATCH] PCI: qcom: Clear ASPM L0s CAP for MSM8996 SoC
On 11/26/25 9:17 AM, Manivannan Sadhasivam wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
>
> Though I couldn't confirm the ASPM L0s support with the Qcom hardware team,
> bug report from Dmitry suggests that L0s is broken on this legacy SoC.
> Hence, clear the L0s CAP for the Root Ports in this SoC.
FWIW if we trust the downstream DT, we have this hunk:
arch/arm64/boot/dts/qcom/msm8996.dtsi
1431: qcom,l1-supported;
1432: qcom,l1ss-supported;
1586: qcom,l1-supported;
1587: qcom,l1ss-supported;
1739: qcom,l1-supported;
1740: qcom,l1ss-supported;
But also funnily enough, msm8996auto boards specifically manually
do a /delete-property/ on those..
(there exists one 'qcom,l0s-supported', but it's NOT set for 8996, 98,
or 845)
On msm-4.14, this became "qcom,no-l0s/l1/l1ss-supported". This forbids L0s
on at least 8150 and 8250.
Later, both hosts on SM8350 and SM8450-PCIe0 (not 1) forbid L0s.
SM8350-PCIe0 sets 'qcom,l1ss-sleep-disable' which influences some RPMh
things, but also prevents some clock ops wrt the CLKREF source
There's probably more platforms affected, this was a quick grep.
Konrad
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