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Message-Id: <20251127125305.89961-1-cuiyunhui@bytedance.com>
Date: Thu, 27 Nov 2025 20:52:57 +0800
From: Yunhui Cui <cuiyunhui@...edance.com>
To: conor@...nel.org,
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palmer@...belt.com,
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Subject: [PATCH v3 0/8] Add NMI Support to RISC-V via SSE
This patchset is based on SSE[1]. It adds support for inter CPU NMI
interfaces, enabling operations such as CPU stopping, backtrace, and
kgdb to be performed via NMI which is a more robust approach compared
to IPI. In addition to inter CPU NMIs, it also adds support for unknown
NMI[2].
v1->v2: Utilized SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED for inter
CPU NMI communication.
v2->v3:
1. Since CPU stop is not a high frequency operation, NMI is directly
used instead of IPI, without first attempting IPI and using NMI as
a fallback.
2. The parameter local_nmi_arg used by sse_event_register cannot represent
local NMI types (Crash, Stop, Backtrace, Kgdb) for multiple CPUs, so a new
per CPU variable local_nmi has been added to address this.
[1] https://lore.kernel.org/all/20251105082639.342973-1-cleger@rivosinc.com/
[2] https://github.com/riscv-non-isa/riscv-sbi-doc/pull/223
Yunhui Cui (8):
drivers: firmware: riscv: add SSE NMI support
riscv: smp: move ipi_cpu_crash_stop() declaration to smp.h
smp: move num_other_online_cpus() into smp.h
riscv: smp: use NMI for crash stop
riscv: smp: use NMI for CPU stop
riscv: smp: use NMI for backtrace
riscv: smp: kgdb: use NMI for CPU roundup
drivers: firmware: riscv: add unknown nmi support
MAINTAINERS | 8 ++
arch/arm64/kernel/smp.c | 11 --
arch/riscv/include/asm/sbi.h | 1 +
arch/riscv/include/asm/smp.h | 11 ++
arch/riscv/kernel/smp.c | 58 ++++----
drivers/firmware/riscv/Kconfig | 10 ++
drivers/firmware/riscv/Makefile | 1 +
drivers/firmware/riscv/riscv_sse_nmi.c | 175 +++++++++++++++++++++++++
include/linux/riscv_sse_nmi.h | 26 ++++
include/linux/smp.h | 11 ++
10 files changed, 277 insertions(+), 35 deletions(-)
create mode 100644 drivers/firmware/riscv/riscv_sse_nmi.c
create mode 100644 include/linux/riscv_sse_nmi.h
--
2.39.5
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