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Message-Id: <20251128050534.437755-4-ekansh.gupta@oss.qualcomm.com>
Date: Fri, 28 Nov 2025 10:35:33 +0530
From: Ekansh Gupta <ekansh.gupta@....qualcomm.com>
To: srini@...nel.org, linux-arm-msm@...r.kernel.org
Cc: gregkh@...uxfoundation.org, quic_bkumar@...cinc.com,
linux-kernel@...r.kernel.org, quic_chennak@...cinc.com,
dri-devel@...ts.freedesktop.org, arnd@...db.de,
dmitry.baryshkov@....qualcomm.com
Subject: [PATCH v4 3/4] misc: fastrpc: Expand context ID mask for DSP polling mode support
Current FastRPC message context uses a 12-bit mask where the upper
8 bits represent the context ID from idr_alloc_cyclic and the lower
4 bits represent the PD type. This layout works for normal FastRPC
calls but fails for polling mode because DSP expects a 16-bit context
with an additional async mode bit. To enable polling mode support
from DSP(DSP writes to poll memory), DSP expects a 16-bit context
where the upper 8 bits are context ID, the lower 4 bits are PD type
and the 5th bit from the end denotes async mode(not yet upstreamed).
If this bit is set, DSP disables polling. With the current design,
odd context IDs set this bit, causing DSP to skip poll memory updates.
Update the context mask to ensure a hole which won't get populated,
ensuring polling mode works as expected. This is not a bug and the
change is added to support polling mode.
Signed-off-by: Ekansh Gupta <ekansh.gupta@....qualcomm.com>
---
drivers/misc/fastrpc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index f7fb44a8e9c0..222ff15e04bd 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -38,7 +38,7 @@
#define FASTRPC_CTX_MAX (256)
#define FASTRPC_INIT_HANDLE 1
#define FASTRPC_DSP_UTILITIES_HANDLE 2
-#define FASTRPC_CTXID_MASK GENMASK(11, 4)
+#define FASTRPC_CTXID_MASK GENMASK(15, 8)
#define INIT_FILELEN_MAX (2 * 1024 * 1024)
#define INIT_FILE_NAMELEN_MAX (128)
#define FASTRPC_DEVICE_NAME "fastrpc"
--
2.34.1
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