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Message-Id: <20251128-qcom_ipq5332_cmnpll-v1-2-55127ba85613@oss.qualcomm.com>
Date: Fri, 28 Nov 2025 00:40:12 -0800
From: Luo Jie <jie.luo@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Luo Jie <quic_luoj@...cinc.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
quic_kkumarcs@...cinc.com, quic_linchen@...cinc.com,
quic_leiwei@...cinc.com, quic_pavir@...cinc.com,
quic_suruchia@...cinc.com, Luo Jie <jie.luo@....qualcomm.com>
Subject: [PATCH 2/5] dt-bindings: clock: qcom: Add CMN PLL support for
IPQ5332 SoC
Add device tree bindings for the CMN PLL block in IPQ5332 SoC, which shares
similarities with IPQ9574 but has different output clock frequencies.
Add a new header file to export CMN PLL output clock specifiers for IPQ5332
SoC.
Signed-off-by: Luo Jie <jie.luo@....qualcomm.com>
---
.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
index 817d51135fbf..5bf29fcd8501 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
@@ -25,6 +25,7 @@ properties:
compatible:
enum:
- qcom,ipq5018-cmn-pll
+ - qcom,ipq5332-cmn-pll
- qcom,ipq5424-cmn-pll
- qcom,ipq9574-cmn-pll
diff --git a/include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h
new file mode 100644
index 000000000000..172330e43669
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ5332_CMN_PLL_CLK 0
+
+/* The output clocks from CMN PLL of IPQ5332. */
+#define IPQ5332_XO_24MHZ_CLK 1
+#define IPQ5332_SLEEP_32KHZ_CLK 2
+#define IPQ5332_PCS_31P25MHZ_CLK 3
+#define IPQ5332_NSS_300MHZ_CLK 4
+#define IPQ5332_PPE_200MHZ_CLK 5
+#define IPQ5332_ETH_50MHZ_CLK 6
+#endif
--
2.43.0
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