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Message-ID: <CAMRc=Mefy=6XDzA2bqe6g_AZS3bbdNEKoq4Z9hV8VwSq5mYBSw@mail.gmail.com>
Date: Fri, 28 Nov 2025 13:11:30 +0100
From: Bartosz Golaszewski <brgl@...nel.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Vinod Koul <vkoul@...nel.org>, Jonathan Corbet <corbet@....net>, 
	Thara Gopinath <thara.gopinath@...il.com>, Herbert Xu <herbert@...dor.apana.org.au>, 
	"David S. Miller" <davem@...emloft.net>, Udit Tiwari <quic_utiwari@...cinc.com>, 
	Daniel Perez-Zoghbi <dperezzo@...cinc.com>, Md Sadre Alam <mdalam@....qualcomm.com>, 
	Dmitry Baryshkov <lumag@...nel.org>, dmaengine@...r.kernel.org, linux-doc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, 
	linux-crypto@...r.kernel.org, 
	Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH v9 11/11] crypto: qce - Switch to using BAM DMA for crypto I/O

On Fri, Nov 28, 2025 at 1:08 PM Konrad Dybcio
<konrad.dybcio@....qualcomm.com> wrote:
>
> On 11/28/25 12:44 PM, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> >
> > With everything else in place, we can now switch to actually using the
> > BAM DMA for register I/O with DMA engine locking.
> >
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> > ---
>
> [...]
>
> > @@ -25,7 +26,7 @@ static inline u32 qce_read(struct qce_device *qce, u32 offset)
> >
> >  static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)
> >  {
> > -     writel(val, qce->base + offset);
> > +     qce_write_dma(qce, offset, val);
> >  }
>
> qce_write() seems no longer useful now
>

I prefer to leave it like this if there are no strong objections. It
reduces the size of the final patch and also - if for any reason in
the future - we need to go back to supporting both DMA and CPU, we
could handle it here.

Bart

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