linux-kernel - RE: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write handlers

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Message-ID:
 <CYYPR11MB8386F204FAE5BB6220944DDC90DCA@CYYPR11MB8386.namprd11.prod.outlook.com>
Date: Fri, 28 Nov 2025 14:16:27 +0000
From: <Prajna.Rajendrakumar@...rochip.com>
To: <andriy.shevchenko@...ux.intel.com>, <linux-spi@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
CC: <broonie@...nel.org>, <Prajna.Rajendrakumar@...rochip.com>,
	<Conor.Dooley@...rochip.com>
Subject: RE: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write
 handlers

> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> Sent: Thursday, November 27, 2025 6:59 PM
> To: Prajna Rajendra kumar - M74368
> <Prajna.Rajendrakumar@...rochip.com>; Andy Shevchenko
> <andriy.shevchenko@...ux.intel.com>; linux-spi@...r.kernel.org; linux-
> kernel@...r.kernel.org
> Cc: Mark Brown <broonie@...nel.org>
> Subject: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write
> handlers
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know
> the content is safe
> 
> Make both handlers to be shorter and easier to understand.
> While at it, unify their style.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@...rochip.com>
> ---
>  drivers/spi/spi-microchip-core-spi.c | 31 +++++++++++-----------------
>  1 file changed, 12 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-
> core-spi.c
> index 08ccdc5f0cc9..439745a36f9c 100644
> --- a/drivers/spi/spi-microchip-core-spi.c
> +++ b/drivers/spi/spi-microchip-core-spi.c
> @@ -97,15 +97,12 @@ static inline void mchp_corespi_read_fifo(struct
> mchp_corespi *spi, u32 fifo_max
>                        MCHP_CORESPI_STATUS_RXFIFO_EMPTY)
>                         ;
> 
> +               /* On TX-only transfers always perform a dummy read */
>                 data = readb(spi->regs + MCHP_CORESPI_REG_RXDATA);
> +               if (spi->rx_buf)
> +                       *spi->rx_buf++ = data;
> 
>                 spi->rx_len--;
> -               if (!spi->rx_buf)
> -                       continue;
> -
> -               *spi->rx_buf = data;
> -
> -               spi->rx_buf++;
>         }
>  }
> 
> @@ -127,23 +124,19 @@ static void mchp_corespi_disable_ints(struct
> mchp_corespi *spi)
> 
>  static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi, u32
> fifo_max)  {
> -       int i = 0;
> -
> -       while ((i < fifo_max) &&
> -              !(readb(spi->regs + MCHP_CORESPI_REG_STAT) &
> -                MCHP_CORESPI_STATUS_TXFIFO_FULL)) {
> -               u32 word;
> -
> -               word = spi->tx_buf ? *spi->tx_buf : 0xaa;
> -               writeb(word, spi->regs + MCHP_CORESPI_REG_TXDATA);
> +       for (int i = 0; i < fifo_max; i++) {
> +               if (readb(spi->regs + MCHP_CORESPI_REG_STAT) &
> +                   MCHP_CORESPI_STATUS_TXFIFO_FULL)
> +                       break;
> 
> +               /* On RX-only transfers always perform a dummy write */
>                 if (spi->tx_buf)
> -                       spi->tx_buf++;
> +                       writeb(*spi->tx_buf++, spi->regs +
> MCHP_CORESPI_REG_TXDATA);
> +               else
> +                       writeb(0xaa, spi->regs +
> + MCHP_CORESPI_REG_TXDATA);
> 
> -               i++;
> +               spi->tx_len--;
>         }
> -
> -       spi->tx_len -= i;
>  }
> 
>  static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
> --
> 2.50.1