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Message-ID: <ed2aaebf-f0ed-4eb6-b880-9c39d4f0533c@oss.qualcomm.com>
Date: Fri, 28 Nov 2025 22:29:32 +0800
From: Jie Luo <jie.luo@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Luo Jie <quic_luoj@...cinc.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
quic_kkumarcs@...cinc.com, quic_linchen@...cinc.com,
quic_leiwei@...cinc.com, quic_pavir@...cinc.com,
quic_suruchia@...cinc.com
Subject: Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock
divider
On 11/28/2025 7:38 PM, Konrad Dybcio wrote:
> On 11/28/25 9:40 AM, Luo Jie wrote:
>> The clk_cmn_pll_recalc_rate() function must account for the reference clock
>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
>> with a reference divider other than 1 calculate incorrect CMN PLL rates.
>> For example, on IPQ5332 where the reference divider is 2, the computed rate
>> becomes twice the actual output.
>>
>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
>> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
>> rate = (parent_rate / ref_div) * 2 * factor.
>>
>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
>> IPQ5424, IPQ5018) that use ref_div = 1.
>
> I'm not sure how to interpret this. Is the value fixed on these platforms
> you mentioned, and always shows up as 0?
>
> Konrad
On these platforms the hardware ref_div register comes up with a value
of 1 by default. It is, however, still a programmable field and not
strictly fixed to 1.
The ref_div == 0 check in this patch is only meant as a safety net to
avoid a divide‑by‑zero in the rate calculation.
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