linux-kernel - RE: [PATCH v4 01/16] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

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Message-ID:
 <TY3PR01MB1134676EBFEF0DDBD1E81912286DCA@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Fri, 28 Nov 2025 15:10:45 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: geert <geert@...ux-m68k.org>, biju.das.au <biju.das.au@...il.com>
CC: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby
	<jirislaby@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
	<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Geert Uytterhoeven
	<geert+renesas@...der.be>, magnus.damm <magnus.damm@...il.com>, wsa+renesas
	<wsa+renesas@...g-engineering.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-serial@...r.kernel.org"
	<linux-serial@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-renesas-soc@...r.kernel.org"
	<linux-renesas-soc@...r.kernel.org>, Conor Dooley
	<conor.dooley@...rochip.com>
Subject: RE: [PATCH v4 01/16] dt-bindings: serial: renesas,rsci: Document
 RZ/G3E support

Hi Geert Uytterhoeven,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 28 November 2025 12:54
> Subject: Re: [PATCH v4 01/16] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> 
> Hi Biju,
> 
> On Tue, 25 Nov 2025 at 16:06, Biju <biju.das.au@...il.com> wrote:
> > From: Biju Das <biju.das.jz@...renesas.com>
> >
> > Add documentation for the serial communication interface (RSCI) found
> > on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is
> > identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage
> > FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode
> > operation. RZ/G3E has 6 clocks(5 module clocks + 1 external clock)
> > compared to 3 clocks
> > (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
> >
> > Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> > ---
> > v3->v4:
> >  * Dropped separate compatible for non-FIFO mode and instead using single
> >    compatible "renesas,r9a09g047-rsci" as non-FIFO mode can be achieved
> >    by software configuration.
> >  * Renamed clock-names bus->pclk
> >  * Rearranged clock-names tclk{4, 16, 64}
> >  * Retained the tag as the changes are trivial.
> 
> Thanks for the update!
> 
> > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> 
> > @@ -62,6 +82,46 @@ required:
> >    - clock-names
> >    - power-domains
> >
> > +allOf:
> > +  - $ref: serial.yaml#
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a09g077-rsci
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 2
> > +          maxItems: 3
> > +
> > +        clock-names:
> > +          minItems: 2
> > +          maxItems: 3
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a09g047-rsci
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 5
> > +          maxItems: 6
> > +
> > +        clock-names:
> > +          minItems: 5
> > +          maxItems: 6
> > +
> > +      required:
> > +        - resets
> > +        - reset-names
> > +    else:
> > +      properties:
> > +        resets: false
> 
> While technically correct, please move the contents of the "else" branch to the "if ...
> renesas,r9a09g077-rsci" above, to increase uniformity.

OK, will move "resets: false" there.

> 
> Also, RZ/G3E RSCI has two more interrupts: AED (active edge detection) and BFD (bus collision
> detection).  Sorry for missing that before.

Oops. Will add this as well.

Cheers,
Biju