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Message-ID: <202511301514.t3OSLc6E-lkp@intel.com>
Date: Sun, 30 Nov 2025 15:38:22 +0800
From: kernel test robot <lkp@...el.com>
To: Anna Maniscalco <anna.maniscalco2000@...il.com>,
Rob Clark <robin.clark@....qualcomm.com>,
Sean Paul <sean@...rly.run>, Konrad Dybcio <konradybcio@...nel.org>,
Akhil P Oommen <akhilpo@....qualcomm.com>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jesszhan0024@...il.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Antonino Maniscalco <antomani103@...il.com>
Cc: oe-kbuild-all@...ts.linux.dev, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, stable@...r.kernel.org,
Anna Maniscalco <anna.maniscalco2000@...il.com>
Subject: Re: [PATCH v2] drm/msm: Fix a7xx per pipe register programming
Hi Anna,
kernel test robot noticed the following build errors:
[auto build test ERROR on 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530]
url: https://github.com/intel-lab-lkp/linux/commits/Anna-Maniscalco/drm-msm-Fix-a7xx-per-pipe-register-programming/20251129-012027
base: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530
patch link: https://lore.kernel.org/r/20251128-gras_nc_mode_fix-v2-1-634cda7b810f%40gmail.com
patch subject: [PATCH v2] drm/msm: Fix a7xx per pipe register programming
config: um-randconfig-002-20251130 (https://download.01.org/0day-ci/archive/20251130/202511301514.t3OSLc6E-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251130/202511301514.t3OSLc6E-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511301514.t3OSLc6E-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/msm/adreno/a6xx_gpu.c: In function 'a6xx_set_ubwc_config':
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:853:36: error: 'A7XX_PIPE_BR' undeclared (first use in this function)
853 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {
| ^~~~~~~~~~~~
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:853:36: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:853:61: error: 'A7XX_PIPE_BV' undeclared (first use in this function)
853 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {
| ^~~~~~~~~~~~
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:860:59: error: 'A7XX_PIPE_NONE' undeclared (first use in this function); did you mean 'MSM_PIPE_NONE'?
860 | A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));
| ^~~~~~~~~~~~~~
| MSM_PIPE_NONE
drivers/gpu/drm/msm/adreno/a6xx_gpu.c: In function 'a7xx_patch_pwrup_reglist':
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:921:36: error: 'A7XX_PIPE_BR' undeclared (first use in this function)
921 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {
| ^~~~~~~~~~~~
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:921:61: error: 'A7XX_PIPE_BV' undeclared (first use in this function)
921 | for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {
| ^~~~~~~~~~~~
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:934:59: error: 'A7XX_PIPE_NONE' undeclared (first use in this function); did you mean 'MSM_PIPE_NONE'?
934 | A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));
| ^~~~~~~~~~~~~~
| MSM_PIPE_NONE
vim +/A7XX_PIPE_BR +853 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
807
808 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
809 {
810 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
811 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config;
812 /*
813 * We subtract 13 from the highest bank bit (13 is the minimum value
814 * allowed by hw) and write the lowest two bits of the remaining value
815 * as hbb_lo and the one above it as hbb_hi to the hardware.
816 */
817 BUG_ON(cfg->highest_bank_bit < 13);
818 u32 hbb = cfg->highest_bank_bit - 13;
819 bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;
820 u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2);
821 bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
822 bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
823 bool min_acc_len_64b = false;
824 u8 uavflagprd_inv = 0;
825 u32 hbb_hi = hbb >> 2;
826 u32 hbb_lo = hbb & 3;
827
828 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))
829 uavflagprd_inv = 2;
830
831 if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu))
832 min_acc_len_64b = true;
833
834 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
835 level2_swizzling_dis << 12 |
836 rgb565_predicator << 11 |
837 hbb_hi << 10 | amsbc << 4 |
838 min_acc_len_64b << 3 |
839 hbb_lo << 1 | ubwc_mode);
840
841 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL,
842 level2_swizzling_dis << 6 | hbb_hi << 4 |
843 min_acc_len_64b << 3 |
844 hbb_lo << 1 | ubwc_mode);
845
846 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
847 level2_swizzling_dis << 12 | hbb_hi << 10 |
848 uavflagprd_inv << 4 |
849 min_acc_len_64b << 3 |
850 hbb_lo << 1 | ubwc_mode);
851
852 if (adreno_is_a7xx(adreno_gpu)) {
> 853 for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) {
854 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
855 A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));
856 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,
857 FIELD_PREP(GENMASK(8, 5), hbb_lo));
858 }
859 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
> 860 A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE));
861 }
862
863 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
864 min_acc_len_64b << 23 | hbb_lo << 21);
865
866 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL,
867 cfg->macrotile_mode);
868 }
869
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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