linux-kernel - [PATCH v2 5/8] drm/msm/dp: Add dpcd link

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Message-ID: <20251201011457.17422-6-daleyo@gmail.com>
Date: Mon,  1 Dec 2025 01:14:46 +0000
From: Dale Whinham <daleyo@...il.com>
To: Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
	Maxime Ripard <mripard@...nel.org>,
	Thomas Zimmermann <tzimmermann@...e.de>,
	David Airlie <airlied@...il.com>,
	Simona Vetter <simona@...ll.ch>,
	Rob Clark <robin.clark@....qualcomm.com>,
	Dmitry Baryshkov <lumag@...nel.org>,
	Abhinav Kumar <abhinav.kumar@...ux.dev>,
	Jessica Zhang <jessica.zhang@....qualcomm.com>,
	Sean Paul <sean@...rly.run>,
	Marijn Suijten <marijn.suijten@...ainline.org>
Cc: Jérôme de Bretagne <jerome.debretagne@...il.com>,
	Dale Whinham <daleyo@...il.com>,
	dri-devel@...ts.freedesktop.org,
	linux-kernel@...r.kernel.org,
	linux-arm-msm@...r.kernel.org,
	freedreno@...ts.freedesktop.org
Subject: [PATCH v2 5/8] drm/msm/dp: Add dpcd link_rate quirk for Surface Pro 11 OLED

From: Jérôme de Bretagne <jerome.debretagne@...il.com>

The Samsung ATNA30DW01-1 OLED panel in Microsoft Surface Pro 11 (Denali)
reports a max link rate value of 0 in the DPCD register, causing the
panel to fail to probe.

Add a quirk for this panel during DPCD read to set the max link rate
to 8.1Gbps (HBR3), which is the expected value as reported by the
"EDPOverrideDPCDCaps" block found in the DSDT (0x1E).

Signed-off-by: Jérôme de Bretagne <jerome.debretagne@...il.com>
Tested-by: Dale Whinham <daleyo@...il.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c |  2 ++
 drivers/gpu/drm/msm/dp/dp_panel.c       | 14 ++++++++++++++
 include/drm/display/drm_dp_helper.h     |  7 +++++++
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 4aaeae4fa03c..a533fbb2988d 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2543,6 +2543,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
 	{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
 	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
+	/* Samsung ATNA30DW01-1 OLED panel in Microsoft Surface Pro 11 reports a DP_MAX_LINK_RATE of 0 */
+	{ OUI(0xBA, 0x41, 0x59), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_8_1_GBPS) },
 };
 
 #undef OUI
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index 15b7f6c7146e..6bcfefd457c4 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -91,6 +91,7 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)
 	int rc, max_lttpr_lanes, max_lttpr_rate;
 	struct msm_dp_panel_private *panel;
 	struct msm_dp_link_info *link_info;
+	struct drm_dp_desc desc;
 	u8 *dpcd, major, minor;
 
 	panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
@@ -99,6 +100,19 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)
 	if (rc)
 		return rc;
 
+	rc = drm_dp_read_desc(panel->aux, &desc, drm_dp_is_branch(dpcd));
+	if (rc)
+		return rc;
+
+	/*
+	 * for some reason the ATNA30DW01-1 OLED panel in Microsoft Surface Pro 11
+	 * reports a max link rate of 0 in the DPCD register. Fix this to match the
+	 * EDPOverrideDPCDCaps value (0x1E) found in the ACPI DSDT
+	 */
+	if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_8_1_GBPS)) {
+		dpcd[1] = DP_LINK_BW_8_1;
+	}
+
 	msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd);
 	link_info = &msm_dp_panel->link_info;
 	link_info->revision = dpcd[DP_DPCD_REV];
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 87caa4f1fdb8..737ec5317666 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -820,6 +820,13 @@ enum drm_dp_quirk {
 	 * requires enabling DSC.
 	 */
 	DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
+	/**
+	 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_8_1_GBPS:
+	 *
+	 * The device supports a link rate of 8.1 Gbps / HBR3 (0x1e) despite
+	 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
+	 */
+	DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_8_1_GBPS,
 };
 
 /**
-- 
2.52.0