linux-kernel - [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM

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Message-Id: <103e156ea1f2201db52034e370a907f46edafb83.1764509485.git.zhouquan@iscas.ac.cn>
Date: Mon,  1 Dec 2025 09:28:25 +0800
From: zhouquan@...as.ac.cn
To: anup@...infault.org,
	ajones@...tanamicro.com,
	atishp@...shpatra.org,
	paul.walmsley@...ive.com,
	palmer@...belt.com
Cc: linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	kvm@...r.kernel.org,
	kvm-riscv@...ts.infradead.org,
	Quan Zhou <zhouquan@...as.ac.cn>
Subject: [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM

From: Quan Zhou <zhouquan@...as.ac.cn>

Extend the KVM ISA extension ONE_REG interface to allow KVM user
space to detect and enable zicfiss/zicfilp exts for Guest/VM,
the rules defined in the spec [1] are as follows:
---
1) Zicfiss extension introduces the SSE field (bit 3) in henvcfg.
If the SSE field is set to 1, the Zicfiss extension is activated
in VS-mode. When the SSE field is 0, the Zicfiss extension remains
inactive in VS-mode.

2) Zicfilp extension introduces the LPE field (bit 2) in henvcfg.
When the LPE field is set to 1, the Zicfilp extension is enabled
in VS-mode. When the LPE field is 0, the Zicfilp extension is not
enabled in VS-mode.

[1] - https://github.com/riscv/riscv-cfi

Signed-off-by: Quan Zhou <zhouquan@...as.ac.cn>
---
 arch/riscv/include/uapi/asm/kvm.h | 2 ++
 arch/riscv/kvm/vcpu.c             | 6 ++++++
 arch/riscv/kvm/vcpu_onereg.c      | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 759a4852c09a..7ca087848a43 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -190,6 +190,8 @@ enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZFBFMIN,
 	KVM_RISCV_ISA_EXT_ZVFBFMIN,
 	KVM_RISCV_ISA_EXT_ZVFBFWMA,
+	KVM_RISCV_ISA_EXT_ZICFILP,
+	KVM_RISCV_ISA_EXT_ZICFISS,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 5ce35aba6069..098d77f9a886 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -557,6 +557,12 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
 	if (riscv_isa_extension_available(isa, ZICBOZ))
 		cfg->henvcfg |= ENVCFG_CBZE;
 
+	if (riscv_isa_extension_available(isa, ZICFILP))
+		cfg->henvcfg |= ENVCFG_LPE;
+
+	if (riscv_isa_extension_available(isa, ZICFISS))
+		cfg->henvcfg |= ENVCFG_SSE;
+
 	if (riscv_isa_extension_available(isa, SVADU) &&
 	    !riscv_isa_extension_available(isa, SVADE))
 		cfg->henvcfg |= ENVCFG_ADUE;
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 865dae903aa0..3d05a4bafd9b 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -72,6 +72,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
 	KVM_ISA_EXT_ARR(ZICBOP),
 	KVM_ISA_EXT_ARR(ZICBOZ),
 	KVM_ISA_EXT_ARR(ZICCRSE),
+	KVM_ISA_EXT_ARR(ZICFILP),
+	KVM_ISA_EXT_ARR(ZICFISS),
 	KVM_ISA_EXT_ARR(ZICNTR),
 	KVM_ISA_EXT_ARR(ZICOND),
 	KVM_ISA_EXT_ARR(ZICSR),
-- 
2.34.1