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Message-ID: <df275a4bbf3fa4d4f0a622cd06d00ebdf847563f.1764592300.git.dan.carpenter@linaro.org>
Date: Mon, 1 Dec 2025 16:08:24 +0300
From: Dan Carpenter <dan.carpenter@...aro.org>
To: Lee Jones <lee@...nel.org>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, NXP S32 Linux Team <s32@....com>,
linaro-s32@...aro.org
Subject: [PATCH 2/4] dt-bindings: mfd: syscon: Document the GPR syscon for
the NXP S32 SoCs
The NXP S32 SoCs have a GPR region which is used by a variety of
drivers. Some examples of the registers in this region are:
* DDR_PMU_IRQ
* GMAC0_PHY_INTF_SEL
* GMAC1_PHY_INTF_SEL
* PFE_EMACS_INTF_SEL
* PFE_COH_EN
* PFE_PWR_CTRL
* PFE_EMACS_GENCTRL1
* PFE_GENCTRL3
Use the syscon interface to access these registers.
Signed-off-by: Dan Carpenter <dan.carpenter@...aro.org>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 55efb83b1495..6e6b92227092 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -102,6 +102,7 @@ select:
- mstar,msc313-pmsleep
- nuvoton,ma35d1-sys
- nuvoton,wpcm450-shm
+ - nxp,s32-gpr
- qcom,apq8064-mmss-sfpb
- qcom,apq8064-sps-sic
- rockchip,px30-qos
@@ -212,6 +213,7 @@ properties:
- mstar,msc313-pmsleep
- nuvoton,ma35d1-sys
- nuvoton,wpcm450-shm
+ - nxp,s32-gpr
- qcom,apq8064-mmss-sfpb
- qcom,apq8064-sps-sic
- rockchip,px30-qos
--
2.51.0
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