linux-kernel - [GIT PULL] RAS for v6.19-rc1

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Message-ID: <20251201141930.GAaS2j8qO6lr3K4KS3@fat_crate.local>
Date: Mon, 1 Dec 2025 15:19:30 +0100
From: Borislav Petkov <bp@...en8.de>
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: x86-ml <x86@...nel.org>, lkml <linux-kernel@...r.kernel.org>
Subject: [GIT PULL] RAS for v6.19-rc1

Hi Linus,

please pull the RAS lineup for v6.19-rc1.

Thx.

---

The following changes since commit 6146a0f1dfae5d37442a9ddcba012add260bceb0:

  Linux 6.18-rc4 (2025-11-02 11:28:02 -0800)

are available in the Git repository at:

  ssh://git@...olite.kernel.org/pub/scm/linux/kernel/git/tip/tip tags/ras_core_for_v6.19_rc1

for you to fetch changes up to 5c4663ed1eac01987a1421f059380db48ab7b1a3:

  x86/mce: Handle AMD threshold interrupt storms (2025-11-21 20:41:10 +0100)

----------------------------------------------------------------
- The second part of the AMD MCA interrupts rework after the last-minute
  show-stopper from the last merge window was sorted out. After this,
  the AMD MCA deferred errors, thresholding and corrected errors
  interrupt handlers use common MCA code and are tightly integrated
  into the core MCA code, thereby getting rid of considerable
  duplication. All culminating into allowing CMCI error thresholding
  storms to be detected at AMD too, using the common infrastructure

- Add support for two new MCA bank bits on AMD Zen6 which denote whether
  the error address logged is a system physical address, which obviates
  the need for it to be translated before further error recovery can be
  done

----------------------------------------------------------------
Avadhut Naik (2):
      x86/mce: Add support for physical address valid bit
      x86/mce: Do not clear bank's poll bit in mce_poll_banks on AMD SMCA systems

Smita Koralahalli (1):
      x86/mce: Handle AMD threshold interrupt storms

Yazen Ghannam (7):
      x86/mce: Unify AMD THR handler with MCA Polling
      x86/mce: Unify AMD DFR handler with MCA Polling
      x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems
      x86/mce/amd: Support SMCA Corrected Error Interrupt
      x86/mce/amd: Remove redundant reset_block()
      x86/mce/amd: Define threshold restart function for banks
      x86/mce: Save and use APEI corrected threshold limit

 arch/x86/include/asm/mce.h          |  14 ++
 arch/x86/kernel/acpi/apei.c         |   2 +
 arch/x86/kernel/cpu/mce/amd.c       | 356 ++++++++++++++----------------------
 arch/x86/kernel/cpu/mce/core.c      |  31 +++-
 arch/x86/kernel/cpu/mce/internal.h  |   4 +
 arch/x86/kernel/cpu/mce/threshold.c |  19 +-
 6 files changed, 210 insertions(+), 216 deletions(-)


-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette