linux-kernel - Re: [net-next PATCH] net: phy: RTL8211FVD: Restore disabling of PHY-mode EEE

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Message-ID: <20251202163837.geymkous5dn76pgh@skbuf>
Date: Tue, 2 Dec 2025 18:38:37 +0200
From: Vladimir Oltean <vladimir.oltean@....com>
To: Ivan Galkin <ivan.galkin@...s.com>
Cc: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
	Marek Vasut <marek.vasut@...lbox.org>,
	Maxime Chevallier <maxime.chevallier@...tlin.com>,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
	kernel@...s.com
Subject: Re: [net-next PATCH] net: phy: RTL8211FVD: Restore disabling of
 PHY-mode EEE

On Tue, Dec 02, 2025 at 10:07:42AM +0100, Ivan Galkin wrote:
> When support for RTL8211F(D)(I)-VD-CG was introduced in commit
> bb726b753f75 ("net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG")
> the implementation assumed that this PHY model doesn't have the
> control register PHYCR2 (Page 0xa43 Address 0x19). This
> assumption was based on the differences in CLKOUT configurations
> between RTL8211FVD and the remaining RTL8211F PHYs. In the latter
> commit 2c67301584f2
> ("net: phy: realtek: Avoid PHYCR2 access if PHYCR2 not present")
> this assumption was expanded to the PHY-mode EEE.
> 
> I performed tests on RTL8211FI-VD-CG and confirmed that disabling
> PHY-mode EEE works correctly and is uniform with other PHYs
> supported by the driver. To validate the correctness,
> I contacted Realtek support. Realtek confirmed that PHY-mode EEE on
> RTL8211F(D)(I)-VD-CG is configured via Page 0xa43 Address 0x19 bit 5.
> 
> Moreover, Realtek informed me that the most recent datasheet
> for RTL8211F(D)(I)-VD-CG v1.1 is incomplete and the naming of
> control registers is partly inconsistent. The errata I
> received from Realtek corrects the naming as follows:
> 
> | Register                | Datasheet v1.1 | Errata |
> |-------------------------|----------------|--------|
> | Page 0xa44 Address 0x11 | PHYCR2         | PHYCR3 |
> | Page 0xa43 Address 0x19 | N/A            | PHYCR2 |
> 
> This information confirms that the supposedly missing control register,
> PHYCR2, exists in the RTL8211F(D)(I)-VD-CG under the same address and
> the same name. It controls widely the same configs as other PHYs from
> the RTL8211F series (e.g. PHY-mode EEE). Clock out configuration is an
> exception.
> 
> Given all this information, restore disabling of the PHY-mode EEE.
> 
> Fixes: 2c67301584f2 ("net: phy: realtek: Avoid PHYCR2 access if PHYCR2 not present")
> Signed-off-by: Ivan Galkin <ivan.galkin@...s.com>
> ---

Makes sense. Thanks for the in-depth analysis.

Reviewed-by: Vladimir Oltean <vladimir.oltean@....com>