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Message-ID: <CA+V-a8skz6D__T3oeTq4vfikkxRKM=6MAEgsu_MK01RqVLrjkA@mail.gmail.com>
Date: Tue, 2 Dec 2025 17:20:31 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Biju <biju.das.au@...il.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby <jirislaby@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, linux-kernel@...r.kernel.org,
linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v5 00/17] Add RZ/G3E RSCI support
Hi Biju,
Thank you for the series.
On Sat, Nov 29, 2025 at 4:43 PM Biju <biju.das.au@...il.com> wrote:
>
> From: Biju Das <biju.das.jz@...renesas.com>
>
> Add RZ/G3E RSCI support for FIFO and non-FIFO mode. RSCI IP found on
> RZ/G3E SoC is similar to one on RZ/T2H, but has 32-stage fifo. RZ/G3E has
> 6 clocks (5 module clocks + 1 external clock) compared to 3 clocks
> (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple
> resets. It has 6 irqs compared to 4 on RZ/T2H. Add support for the hardware
> flow control.
>
> v4->v5:
> * Updated commit description related to IRQ difference in binding patch.
> * Dropped the tag for binding patch as there are new changes.
> * Added aed and bfd irqs for RZ/G3E.
> * Moved reset: false to RZ/T2H SoC and dropped the else part for RZ/G3E.
> * Updated conditional schema with interrupts and interrupts-names.
> * Added new patch for set_rtrg() callback.
> * Dropped checking port type for device file{create, remove} and instead
> started checking the fifosize.
> * Dropped sci_is_fifo_type() helper.
> * Renamed rsci_port_params->rsci_rzt2h_port_params.
> * Renamed rsci_rzg3e_scif_port_params->rsci_rzg3e_port_params.
> v3->v4:
> * Collected tags.
> * Dropped separate compatible for non-FIFO mode and instead using single
> compatible "renesas,r9a09g047-rsci" as non-FIFO mode can be achieved
> by software configuration.
> * Dropped the non-FIFO mode support and will add this support later.
> * Renamed clock-names from bus->pclk
> * Rearranged the clock-names tclk{4, 16, 64}
> * Added separate patch for sci_is_fifo_type() covering all SoCs that has
> FIFO.
> * Updated commit header and description for patch#{3,9,16}
> * Dropped rsci_clear_SCxSR() instead of rsci_clear_CFC() as it clears the
> CFCLR register.
> * Added separate patch for updating t2h rx_trigger size from 15->16.
> * Added separate patch for renaming port SCI_PORT_RSCI->RSCI_PORT_SCIF16.
> * Dropped enum RSCI_PORT_SCI
> * Replaced the enum RSCI_PORT_SCIF->RSCI_PORT_SCIF32
> * Moved rx_trigger update to later patch#16.
> * Reduced the checks in sci_init_clocks() by avoid looking up clocks that
> are not relevant for the port.
> * Added separate patch for updating early_console data and callback()
> names.
> * Updated rsci_type() to drop "scif" type instead use "rsci"
> * Replaced the compatible "renesas,r9a09g047-rscif" with
> "renesas,r9a09g047-rsci"
> * Renamed the port enum from RSCI_PORT_SCIF->RSCI_PORT_SCIF32.
> * Renamed of_rsci_scif_data->of_rsci_rzg3e_data
> * Renamed the funvtion rsci_rzg3e_scif_early_console_setup() with
> rsci_rzg3e_early_console_setup().
> v2->v3:
> * Dropped 1st and 3rd items from clk-names and added minItems for the
> range for the binding patch.
> * Added minItems for clk and clk-names for RZ/T2H as the range is 2-3
> * Added maxItems for clk and clk-names for RZ/G3E as the range is 5-6
> * Retained the tag as it is trivial change.
> * Updated dev_err_probe() in sci_init_clocks() as it fits in 100-column
> limit.
> * Dropped cpu_relax() from rsci_finish_console_write() and added a
> comment.
> * Added sci_is_rsci_fifo_type() helper for reuse in probe() and remove().
> v1->v2:
> * Updated commit message for patch#1,#3,#9
> * Added resets:false for non RZ/G3E SoCs in bindings.
> * Increased line limit for error messages to 100-column limit for patch#3
> * Updated multiline comment to fit into single line.
> * Updated set_termios() for getting baud_rate()
>
> Biju Das (17):
> dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> serial: sh-sci: Update rx_trigger size for RZ/T2H RSCI
> serial: rsci: Add set_rtrg() callback
> serial: sh-sci: Drop checking port type for device file{create,
> remove}
> serial: rsci: Drop rsci_clear_SCxSR()
> serial: sh-sci: Drop extra lines
> serial: rsci: Drop unused macro DCR
> serial: rsci: Drop unused TDR register
> serial: sh-sci: Use devm_reset_control_array_get_exclusive()
> serial: sh-sci: Add sci_is_rsci_type()
> serial: sh-sci: Rename port SCI_PORT_RSCI->RSCI_PORT_SCIF16
> serial: sh-sci: Add RSCI_PORT_SCIF32 port ID
> serial: sh-sci: Add support for RZ/G3E RSCI clks
> serial: sh-sci: Make sci_scbrr_calc() public
> serial: sh-sci: Add finish_console_write() callback
> serial: rsci: Rename early_console data, port_params and callback()
> names
> serial: sh-sci: Add support for RZ/G3E RSCI
>
> .../bindings/serial/renesas,rsci.yaml | 99 +++++-
> drivers/tty/serial/rsci.c | 310 ++++++++++++++++--
> drivers/tty/serial/rsci.h | 3 +-
> drivers/tty/serial/sh-sci-common.h | 10 +-
> drivers/tty/serial/sh-sci.c | 80 +++--
> 5 files changed, 422 insertions(+), 80 deletions(-)
>
Tested on RZ/V2H and RZ/V2N EVKs,
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Cheers,
Prabhakar
> --
> 2.43.0
>
>
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