linux-kernel - [PATCH 0/1] riscv: Optimize signal handling with sum enabled accesses

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Message-Id: <20251202074303.81485-1-maohan4761@gmail.com>
Date: Tue,  2 Dec 2025 15:43:02 +0800
From: maohan4761@...il.com
To: pjw@...nel.org,
	palmer@...belt.com
Cc: guoren@...nel.org,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Mao Han <han_mao@...ux.alibaba.com>
Subject: [PATCH 0/1] riscv: Optimize signal handling with sum enabled accesses

From: Mao Han <han_mao@...ux.alibaba.com>

Currently, the signal function frequently toggles the SUM bit to control
user-space access within __get_user/__put_user.

        void __user *sc_ext_ptr = &sc->sc_extdesc.hdr;
ffffffff80005904:       44898a13                addi    s4,s3,1096
                err |= __get_user(magic, &head->magic);
ffffffff80005908:       8752                    mv      a4,s4
ffffffff8000590a:       00000013                nop
ffffffff8000590e:       1004a073                csrs    sstatus,s1
ffffffff80005912:       4781                    li      a5,0
ffffffff80005914:       4310                    lw      a2,0(a4)
ffffffff80005916:       2601                    sext.w  a2,a2
ffffffff80005918:       1004b073                csrc    sstatus,s1
                err |= __get_user(size, &head->size);
ffffffff8000591c:       004a0693                addi    a3,s4,4
ffffffff80005920:       00000013                nop
ffffffff80005924:       1004a073                csrs    sstatus,s1
ffffffff80005928:       4701                    li      a4,0
ffffffff8000592a:       428c                    lw      a1,0(a3)
ffffffff8000592c:       86ae                    mv      a3,a1
ffffffff8000592e:       2581                    sext.w  a1,a1
ffffffff80005930:       1004b073                csrc    sstatus,s1
ffffffff80005934:       8fd9                    or      a5,a5,a4

On modern out-of-order processors, frequent CSR (Control and Status Register)
operations introduce pipeline stalls, significantly degrading performance.

This patch attempts to enable the SUM bit only once at the beginning of
rt_sigreturn and setup_rt_frame, keep it enabled throughout frame handling,
and directly access user-space memory without repeatedly toggling the SUM bit.
This reduces the overhead caused by frequent CSR state changes.

Lmbench signal-related benchmarks show approximately a 20% performance improvement.

Mao Han (1):
  riscv: Optimize signal handling with sum enabled accesses

 arch/riscv/include/asm/uaccess.h | 75 ++++++++++++++++++++++++++++++++
 arch/riscv/kernel/signal.c       | 74 +++++++++++++++++++------------
 2 files changed, 121 insertions(+), 28 deletions(-)

-- 
2.25.1