linux-kernel - Re: [PATCH 15/19] coresight: trbe: Add static key for bypassing trigger mode

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Message-ID: <47da45df-b75f-46e8-9839-97d869b43afc@arm.com>
Date: Tue, 2 Dec 2025 12:10:22 +0000
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Leo Yan <leo.yan@....com>, Mike Leach <mike.leach@...aro.org>,
 James Clark <james.clark@...aro.org>,
 Anshuman Khandual <anshuman.khandual@....com>,
 Yeoreum Yun <yeoreum.yun@....com>, Will Deacon <will@...nel.org>,
 Mark Rutland <mark.rutland@....com>, Tamas Petz <tamas.petz@....com>,
 Tamas Zsoldos <tamas.zsoldos@....com>,
 Arnaldo Carvalho de Melo <acme@...nel.org>,
 Namhyung Kim <namhyung@...nel.org>, Jiri Olsa <jolsa@...nel.org>,
 Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>
Cc: coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org
Subject: Re: [PATCH 15/19] coresight: trbe: Add static key for bypassing
 trigger mode

On 01/12/2025 11:22, Leo Yan wrote:
> To avoid complexity, if any CPU in the system has the fill mode erratum,
> the driver will not use trigger mode, it simply rolls back to fill mode
> only and apply the workaround on it.
> 
> Add a static key to control trigger mode bypassing.  During each CPU
> probe, the key is enabled when the relevant erratum is detected.
> 
> Signed-off-by: Leo Yan <leo.yan@....com>
> ---
>   drivers/hwtracing/coresight/coresight-trbe.c | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 941aa46e9b11f60c707eb40093964de454a3fd83..8390d0a8fe23d35945610df15f21751279ee37ee 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -17,6 +17,7 @@
>   
>   #include <asm/barrier.h>
>   #include <asm/cpufeature.h>
> +#include <linux/jump_label.h>
>   #include <linux/kvm_host.h>
>   #include <linux/vmalloc.h>
>   
> @@ -147,6 +148,12 @@ struct trbe_drvdata {
>   	struct platform_device *pdev;
>   };
>   
> +DEFINE_STATIC_KEY_FALSE(trbe_trigger_mode_bypass);
> +
> +#define trbe_trigger_mode_need_bypass(cpudata)		\
> +	(trbe_may_overwrite_in_fill_mode((cpudata)) ||	\
> +	 trbe_may_write_out_of_range((cpudata)))
> +

Please make that a static inline function.

>   static void trbe_check_errata(struct trbe_cpudata *cpudata)
>   {
>   	int i;
> @@ -1306,6 +1313,14 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp
>   
>   	dev_set_drvdata(&trbe_csdev->dev, cpudata);
>   	coresight_set_percpu_sink(cpu, trbe_csdev);
> +
> +	/*
> +	 * If any CPU cannot use trigger mode, bypass the mode globally for
> +	 * consistent tracing behaviour.
> +	 */
> +	if (trbe_trigger_mode_need_bypass(cpudata))
> +		static_branch_enable(&trbe_trigger_mode_bypass);

You only need to enable this once, not for every CPU.

Suzuki


> +
>   	return;
>   cpu_clear:
>   	cpumask_clear_cpu(cpu, &drvdata->supported_cpus);
>