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Message-ID: <8ff6ab79-a3d3-48e3-9340-8b91a9ce1b27@linaro.org>
Date: Tue, 2 Dec 2025 15:59:03 +0200
From: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
To: Vikram Sharma <quic_vikramsa@...cinc.com>, rfoss@...nel.org,
todor.too@...il.com, bryan.odonoghue@...aro.org, mchehab@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
andersson@...nel.org, konradybcio@...nel.org, hverkuil-cisco@...all.nl,
cros-qcom-dts-watchers@...omium.org, catalin.marinas@....com, will@...nel.org
Cc: linux-arm-kernel@...ts.infradead.org, nihalkum@....qualcomm.com,
linux-media@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Ravi Shankar <quic_rshankar@...cinc.com>,
Vishal Verma <quic_vishverm@...cinc.com>,
Suresh Vankadara <quic_svankada@...cinc.com>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v6 2/3] arm64: dts: qcom: qcs8300: Add CCI definitions
On 11/26/25 10:10, Vikram Sharma wrote:
> From: Nihal Kumar Gupta <quic_nihalkum@...cinc.com>
>
> Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI).
> Compared to Lemans, the key difference is in SDA/SCL GPIO assignments
> and number of CCIs.
>
> Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@...cinc.com>
> Co-developed-by: Ravi Shankar <quic_rshankar@...cinc.com>
> Signed-off-by: Ravi Shankar <quic_rshankar@...cinc.com>
> Co-developed-by: Vishal Verma <quic_vishverm@...cinc.com>
> Signed-off-by: Vishal Verma <quic_vishverm@...cinc.com>
> Co-developed-by: Suresh Vankadara <quic_svankada@...cinc.com>
> Signed-off-by: Suresh Vankadara <quic_svankada@...cinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@...cinc.com>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/monaco.dtsi | 345 +++++++++++++++++++++++++++
> 1 file changed, 345 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index 774255c3f6fc..7c575e1c5e10 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -4776,6 +4776,117 @@ videocc: clock-controller@...0000 {
> #power-domain-cells = <1>;
> };
>
> + cci0: cci@...3000 {
> + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac13000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_0_CLK>;
> + clock-names = "cpas_ahb",
> + "cci";
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci0_0_default &cci0_1_default>;
> + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci0_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci0_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci1: cci@...4000 {
> + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac14000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_1_CLK>;
> + clock-names = "cpas_ahb",
> + "cci";
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci1_0_default &cci1_1_default>;
> + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci1_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci1_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci2: cci@...5000 {
> + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac15000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_2_CLK>;
> + clock-names = "cpas_ahb",
> + "cci";
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci2_0_default &cci2_1_default>;
> + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci2_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci2_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> camss: isp@...8000 {
> compatible = "qcom,qcs8300-camss";
>
> @@ -5071,6 +5182,240 @@ tlmm: pinctrl@...0000 {
> #interrupt-cells = <2>;
> wakeup-parent = <&pdc>;
>
> + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state {
> + pins = "gpio73";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam0_default: cam0-default-state {
> + pins = "gpio67";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state {
> + pins = "gpio74";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam1_default: cam1-default-state {
> + pins = "gpio68";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
MCLK pad function declatarions has nothing in common with the CCI, thus it
should be split into a separate commit.
> +
> + cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state {
> + pins = "gpio75";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
All declarations of GPIOs to enable regulators shall be moved to a board
specific .dts file.
--
Best wishes,
Vladimir
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