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Message-ID: <CAP-5=fWmyyp2HTwOtbcJbSR1OO3qCh+sqdua=QmwNa04k8sS6w@mail.gmail.com>
Date: Wed, 3 Dec 2025 15:23:21 -0800
From: Ian Rogers <irogers@...gle.com>
To: Manuel Hernández | OPENCHIP <manuel.hernandez@...nchip.com>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>, Palmer Dabbelt <palmer@...belt.com>,
"linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>, Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>,
Adrian Hunter <adrian.hunter@...el.com>, Paul Walmsley <pjw@...nel.org>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
Samuel Holland <samuel.holland@...ive.com>, Eric Lin <eric.lin@...ive.com>,
Inochi Amaoto <inochiama@...il.com>, open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] perf vendor events riscv: Add CVA6 JSON file
On Tue, Dec 2, 2025 at 10:04 AM Manuel Hernández | OPENCHIP
<manuel.hernandez@...nchip.com> wrote:
>
> From: Manuel Hernández Méndez <manuel.hernandez@...nchip.com>
>
> This patch add the CVA6 JSON file.
>
> Signed-off-by: Manuel Hernández Méndez <manuel.hernandez@...nchip.com>
> ---
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
> .../arch/riscv/openhwgroup/cva6/firmware.json | 68 +++++++++++++++++++
> .../riscv/openhwgroup/cva6/instructions.json | 42 ++++++++++++
> .../arch/riscv/openhwgroup/cva6/memory.json | 52 ++++++++++++++
> .../riscv/openhwgroup/cva6/microarch.json | 22 ++++++
> 5 files changed, 185 insertions(+)
> create mode 100755 tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json
>
> diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> index d5eea7f9aa9a..87cfb0e0849f 100644
> --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> @@ -21,5 +21,6 @@
> 0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core
> 0x5b7-0x0-0x0,v1,thead/c900-legacy,core
> 0x5b7-0x80000000090c0d00-0x2047000,v1,thead/c900-legacy,core
> +0x602-0x3-0x0,v1,openhwgroup/cva6,core
> 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
> 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
> diff --git a/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json
> new file mode 100755
> index 000000000000..7149caec4f80
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json
> @@ -0,0 +1,68 @@
> +[
> + {
> + "ArchStdEvent": "FW_MISALIGNED_LOAD"
> + },
> + {
> + "ArchStdEvent": "FW_MISALIGNED_STORE"
> + },
> + {
> + "ArchStdEvent": "FW_ACCESS_LOAD"
> + },
> + {
> + "ArchStdEvent": "FW_ACCESS_STORE"
> + },
> + {
> + "ArchStdEvent": "FW_ILLEGAL_INSN"
> + },
> + {
> + "ArchStdEvent": "FW_SET_TIMER"
> + },
> + {
> + "ArchStdEvent": "FW_IPI_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_IPI_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_FENCE_I_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_FENCE_I_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json
> new file mode 100644
> index 000000000000..3652970cde8b
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json
> @@ -0,0 +1,42 @@
> +[
> + {
> + "EventName": "EXCEPTIONS",
> + "EventCode": "0x7",
> + "BriefDescription": "valid exceptions encountered"
> + },
> + {
> + "EventName": "EXCEPTION_HANDLER_RETURNS",
> + "EventCode": "0x8",
> + "BriefDescription": "return from an exception"
> + },
> + {
> + "EventName": "BRANCH_INSTRUCTIONS",
> + "EventCode": "0x9",
> + "BriefDescription": "number of branch instructions encountered"
> + },
> + {
> + "EventName": "CALL",
> + "EventCode": "0xC",
> + "BriefDescription": "number of call instructions"
> + },
> + {
> + "EventName": "RETURN",
> + "EventCode": "0xD",
> + "BriefDescription": "number of return instructions"
> + },
> + {
> + "EventName": "INSTRUCTION_FETCH_EMPTY",
> + "EventCode": "0xF",
> + "BriefDescription": "number of invalid instructions in IF"
> + },
> + {
> + "EventName": "INTEGER_INSTRUCTIONS",
> + "EventCode": "0x14",
> + "BriefDescription": "number of integer instructions"
> + },
Is this retired instructions or does it also include speculative
instructions? Perhaps you could add a little more detail to the
descriptions.
Thanks,
Ian
> + {
> + "EventName": "FLOATING_POINT_INSTRUCTIONS",
> + "EventCode": "0x15",
> + "BriefDescription": "number of floating point instructions"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json
> new file mode 100644
> index 000000000000..4509ecfc7bc0
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json
> @@ -0,0 +1,52 @@
> +[
> + {
> + "EventName": "L1_I_CACHE_MISSES",
> + "EventCode": "0x1",
> + "BriefDescription": "number of misses in L1 I-Cache"
> + },
> + {
> + "EventName": "L1_D_CACHE_MISSES",
> + "EventCode": "0x2",
> + "BriefDescription": "number of misses in L1 D-Cache"
> + },
> + {
> + "EventName": "ITLB_MISSES",
> + "EventCode": "0x3",
> + "BriefDescription": "number of misses in ITLB"
> + },
> + {
> + "EventName": "DTLB_MISSES",
> + "EventCode": "0x4",
> + "BriefDescription": "number of misses in DTLB"
> + },
> + {
> + "EventName": "LOAD_ACCESSES",
> + "EventCode": "0x5",
> + "BriefDescription": "number of data memory loads"
> + },
> + {
> + "EventName": "STORE_ACCESSES",
> + "EventCode": "0x6",
> + "BriefDescription": "number of data memory stores"
> + },
> + {
> + "EventName": "L1_I_CACHE_ACCESSES",
> + "EventCode": "0x10",
> + "BriefDescription": "number of accesses to instruction cache"
> + },
> + {
> + "EventName": "L1_D_CACHE_ACCESSES",
> + "EventCode": "0x11",
> + "BriefDescription": "number of accesses to data cache"
> + },
> + {
> + "EventName": "L1_CACHE_LINE_EVICTION",
> + "EventCode": "0x12",
> + "BriefDescription": "number of data cache line eviction"
> + },
> + {
> + "EventName": "ITLB_FLUSH",
> + "EventCode": "0x13",
> + "BriefDescription": "number of ITLB flushes"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json
> new file mode 100644
> index 000000000000..58fe0d04133e
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json
> @@ -0,0 +1,22 @@
> +[
> + {
> + "EventName": "BRANCH_MISPREDICTS",
> + "EventCode": "0xA",
> + "BriefDescription": "number of branch mispredictions"
> + },
> + {
> + "EventName": "BRANCH_EXCEPTIONS",
> + "EventCode": "0xB",
> + "BriefDescription": "number of valid branch exceptions"
> + },
> + {
> + "EventName": "MSB_FULL",
> + "EventCode": "0xE",
> + "BriefDescription": "scoreboard is full"
> + },
> + {
> + "EventName": "PIPELINE_STALL",
> + "EventCode": "0x16",
> + "BriefDescription": "number of cycles the pipeline is stalled during read operands"
> + }
> +]
> --
> 2.34.1
>
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