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Message-Id: <20251204-phy-hdptx-pll-fix-v1-0-d94fd6cfd59b@collabora.com>
Date: Thu, 04 Dec 2025 01:54:08 +0200
From: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
To: Vinod Koul <vkoul@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Heiko Stuebner <heiko@...ech.de>, Dmitry Baryshkov <lumag@...nel.org>
Cc: kernel@...labora.com, linux-phy@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 0/2] Fixup HDMI PLL for phy-rockchip-samsung-hdptx
The Samsung HDMI/eDP TX PHY is currently not able to provide an accurate
enough PLL output frequency to match the TMDS rate of a 1080p@...Hz
display mode, when used with 10 bpc RGB.
This patch set adds a new entry to the TMDS configuration table,
providing the necessary frequency division coefficients for the PHY PLL
to generate the expected 461.101250 MHz output.
Additionally, it drops a bunch of unused members from struct
ropll_config and makes the configuration table more readable.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
---
Cristian Ciocaltea (2):
phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output
phy: rockchip: samsung-hdptx: Cleanup TMDS PLL config table
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 79 +++++++----------------
1 file changed, 24 insertions(+), 55 deletions(-)
---
base-commit: b2c27842ba853508b0da00187a7508eb3a96c8f7
change-id: 20251204-phy-hdptx-pll-fix-0787c92e0cfe
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