linux-kernel - Re: [PATCH V3 3/3] arm64: dts: nvidia: Add nodes for CMDQV

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Message-ID: <516f57b2-cdf1-435c-8de4-978ac8b03f62@nvidia.com>
Date: Wed, 3 Dec 2025 10:44:43 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Ashish Mhetre <amhetre@...dia.com>, will@...nel.org,
 robin.murphy@....com, joro@...tes.org, robh@...nel.org, krzk+dt@...nel.org,
 conor+dt@...nel.org, nicolinc@...dia.com
Cc: thierry.reding@...il.com, vdumpa@...dia.com, jgg@...pe.ca,
 linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-tegra@...r.kernel.org
Subject: Re: [PATCH V3 3/3] arm64: dts: nvidia: Add nodes for CMDQV



On 01/12/2025 16:32, Ashish Mhetre wrote:
> The Command Queue Virtualization (CMDQV) hardware is part of the
> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
> virtualizing the command queue for the SMMU.
> 
> Update SMMU compatible strings to use nvidia,tegra264-smmu to enable
> CMDQV support. Add device tree nodes for the CMDQV hardware and enable
> them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU
> instance is paired with its corresponding CMDQV instance via the
> nvidia,cmdqv property.
> 
> Signed-off-by: Ashish Mhetre <amhetre@...dia.com>
> ---
>   .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi |  8 +++
>   arch/arm64/boot/dts/nvidia/tegra264.dtsi      | 55 +++++++++++++++++--
>   2 files changed, 58 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> index 06795c82427a..7e2c3e66c2ab 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> @@ -23,8 +23,16 @@ iommu@...0000 {
>   			status = "okay";
>   		};
>   
> +		cmdqv@...0000 {
> +			status = "okay";
> +		};
> +
>   		iommu@...0000 {
>   			status = "okay";
>   		};
> +
> +		cmdqv@...0000 {
> +			status = "okay";
> +		};
>   	};
>   };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index f137565da804..5124715caeb3 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3361,7 +3361,7 @@ bus@...0000000 {
>   			 <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
>   
>   		smmu1: iommu@...0000 {
> -			compatible = "arm,smmu-v3";
> +			compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
>   			reg = <0x00 0x5000000 0x0 0x200000>;
>   			interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
>   				     <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
> @@ -3370,10 +3370,19 @@ smmu1: iommu@...0000 {
>   
>   			#iommu-cells = <1>;
>   			dma-coherent;
> +			nvidia,cmdqv = <&cmdqv1>;
> +		};
> +
> +		cmdqv1: cmdqv@...0000 {
> +			compatible = "nvidia,tegra264-cmdqv";
> +			status = "disabled";
> +
> +			reg = <0x00 0x5200000 0x0 0x830000>;
> +			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

Like for other devices, the typical ordering is ...

  compatible = "nvidia,tegra264-cmdqv";
  reg = <0x00 0x5200000 0x0 0x830000>;
  interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  status = "disabled";

So let's follow the same approach here.

Jon

-- 
nvpublic