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Message-ID: <871plbn7vb.fsf@stealth>
Date: Wed, 03 Dec 2025 11:05:12 +0000
From: Punit Agrawal <punit.agrawal@....qualcomm.com>
To: Sudeep Holla <sudeep.holla@....com>
Cc: Punit Agrawal <punit.agrawal@....qualcomm.com>, jassisinghbrar@...il.com,
linux-acpi@...r.kernel.org, linux-kernel@...r.kernel.org,
Jamie Iles <jamie.iles@....qualcomm.com>
Subject: Re: [PATCH] mailbox: pcc: don't zero error register
Sudeep Holla <sudeep.holla@....com> writes:
> On Wed, Nov 05, 2025 at 02:42:29PM +0000, Punit Agrawal wrote:
>> From: Jamie Iles <jamie.iles@....qualcomm.com>
>>
>> The error status mask for a type 3/4 subspace is used for reading the
>> error status, and the bitwise inverse is used for clearing the error
>> with the intent being to preserve any of the non-error bits. However,
>> we were previously applying the mask to extract the status and then
>> applying the inverse to the result which ended up clearing all bits.
>>
>> Instead, store the inverse mask in the preserve mask and then use that
>> on the original value read from the error status so that only the error
>> is cleared.
>>
>> Fixes: c45ded7e1135 ("mailbox: pcc: Add support for PCCT extended PCC subspaces(type 3/4)")
>
> Good catch!
>
> Reviewed-by: Sudeep Holla <sudeep.holla@....com>
Thanks! It looks like Jassi picked up the patch as a fix for v6.18.
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