linux-kernel - Re: [PATCH] arm64: dts: qcom: sm8750: Add camera clock controller

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Message-ID: <3e1d1dc4-7b94-47df-b4bd-f6ce4d7842dd@linaro.org>
Date: Wed, 3 Dec 2025 16:03:26 +0200
From: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
To: Taniya Das <taniya.das@....qualcomm.com>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: Ajit Pandey <ajit.pandey@....qualcomm.com>,
 Imran Shaik <imran.shaik@....qualcomm.com>,
 Jagadeesh Kona <jagadeesh.kona@....qualcomm.com>,
 linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sm8750: Add camera clock controller

Hi Taniya.

On 12/3/25 12:32, Taniya Das wrote:
> Add the camcc clock controller device node for SM8750 SoC.
> 
> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8750.dtsi | 35 ++++++++++++++++++++++++++++++++++-
>   1 file changed, 34 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 3f0b57f428bbb388521c27d9ae96bbef3d62b2e2..f09cec6358806f21827e68e365b492e563c0689a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -2,7 +2,8 @@
>   /*
>    * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>    */
> -
> +#include <dt-bindings/clock/qcom,sm8750-cambistmclkcc.h>
> +#include <dt-bindings/clock/qcom,sm8750-camcc.h>
>   #include <dt-bindings/clock/qcom,rpmh.h>
>   #include <dt-bindings/clock/qcom,sm8750-gcc.h>
>   #include <dt-bindings/clock/qcom,sm8750-tcsr.h>

Please keep the list of included headers ordered.

> @@ -2046,6 +2047,22 @@ aggre2_noc: interconnect@...0000 {
>   			clocks = <&rpmhcc RPMH_IPA_CLK>;
>   		};
>   
> +		cambistmclkcc: clock-controller@...0000 {
> +		       compatible = "qcom,sm8750-cambistmclkcc";
> +		       reg = <0x0 0x1760000 0x0 0x6000>;
> +		       clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK> ,
> +				<&bi_tcxo_div2>,
> +				<&bi_tcxo_ao_div2>,
> +				<&sleep_clk>;
> +			power-domains = <&rpmhpd RPMHPD_MMCX>,
> +					<&rpmhpd RPMHPD_MX>;
> +			required-opps = <&rpmhpd_opp_low_svs>,
> +					<&rpmhpd_opp_low_svs>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;

I've briefly checked the recently sent driver, and I didn't find that this
clock controller serves as a reset controller or a power domain controller.

And if so, these properties shall be obviously removed.

> +		};
> +
>   		mmss_noc: interconnect@...0000 {
>   			compatible = "qcom,sm8750-mmss-noc";
>   			reg = <0x0 0x01780000 0x0 0x5b800>;
> @@ -2740,6 +2757,22 @@ usb_dwc3_ss: endpoint {
>   			};
>   		};
>   
> +		camcc: clock-controller@...0000 {
> +			compatible = "qcom,sm8750-camcc";
> +			reg = <0x0 0xade0000 0x0 0x20000>;
> +			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
> +				 <&bi_tcxo_div2>,
> +				 <&bi_tcxo_ao_div2>,
> +				 <&sleep_clk>;
> +			power-domains = <&rpmhpd RPMHPD_MMCX>,
> +					<&rpmhpd RPMHPD_MXC>;
> +			required-opps = <&rpmhpd_opp_low_svs>,
> +					<&rpmhpd_opp_low_svs>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>   		pdc: interrupt-controller@...0000 {
>   			compatible = "qcom,sm8750-pdc", "qcom,pdc";
>   			reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
> 

-- 
Best wishes,
Vladimir